scholarly journals Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-IQ All-in-One Bandgap Comparator

2021 ◽  
Author(s):  
Van Ha Nguyen
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Accuracy ◽  
Bandgap Reference ◽  
Temperature Range ◽  
Static Power ◽  
Protection Circuits ◽  
Simulation Results ◽  
Low Iq ◽  
Soi Technology

This paper presents a novel and compact bandgap comparator (BGRCOMP) for under-voltage lockout (UVLO) and thermal shutdown (TSD) protection circuits. The proposed BGRCOMP is self-referenced and combines the advantages of both a high-accuracy bandgap reference and a comparator into one single circuit. A latch-controlled biasing technique is also presented, which reduces static power consumption of the proposed BGRCOMP. The proposed BGRCOMP is used for the design of compact and low power UVLO and TSD circuits. The post-layout simulation results using a 0.18 µm BCD-on-SOI technology prove the attractive performance of the UVLO and TSD with a static current (I<sub>Q</sub>) of 7.76 µA and 5.4 µA from a 5 V supply, respectively. The deviations of UVLO thresholds are less than 3 mV in the temperature range of -40~85 °C.

scholarly journals Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-IQ All-in-One Bandgap Comparator

2021 ◽  
Author(s):  
Van Ha Nguyen
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Accuracy ◽  
Bandgap Reference ◽  
Temperature Range ◽  
Static Power ◽  
Protection Circuits ◽  
Simulation Results ◽  
Low Iq ◽  
Soi Technology

This paper presents a novel and compact bandgap comparator (BGRCOMP) for under-voltage lockout (UVLO) and thermal shutdown (TSD) protection circuits. The proposed BGRCOMP is self-referenced and combines the advantages of both a high-accuracy bandgap reference and a comparator into one single circuit. A latch-controlled biasing technique is also presented, which reduces static power consumption of the proposed BGRCOMP. The proposed BGRCOMP is used for the design of compact and low power UVLO and TSD circuits. The post-layout simulation results using a 0.18 µm BCD-on-SOI technology prove the attractive performance of the UVLO and TSD with a static current (I<sub>Q</sub>) of 7.76 µA and 5.4 µA from a 5 V supply, respectively. The deviations of UVLO thresholds are less than 3 mV in the temperature range of -40~85 °C.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Research on Embedded Roundness Measuring System

2012 ◽  
Vol 184-185 ◽  
pp. 1613-1617
Author(s):  
Jin Fang Zhu
Keyword(s):  
Data Collection ◽  
Power Consumption ◽  
Low Power ◽  
High Accuracy ◽  
Measuring System ◽  
Low Power Consumption ◽  
Measurement Principle ◽  
Graphic Construction ◽  
Collection Date ◽  
Roundness Measurement

This article studies the embedded SPC and its application in roundness measuring system by analyzing the current roundness measurement principle and technology. With analyzing the process of data collection, date treatment and various kinds of tool graphic construction, we study the feasibility of integrating SPC into roundness measurement and finally apply the embedded SPC as pure software into roundness measuring system. We design the roundness measuring system based on embedded SPC and develop the roundness measuring system of low power consumption, high accuracy and easy application, which is suitable for industry field usage.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

Load-Balanced Low-Power Routing Algorithm Design for Wireless Sensor Networks

2014 ◽  
Vol 926-930 ◽  
pp. 3641-3644
Author(s):  
Bo He
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Power Consumption ◽  
Low Power ◽  
Routing Algorithm ◽  
Algorithm Design ◽  
Wireless Sensor ◽  
Load Factor ◽  
Simulation Results ◽  
Load Balanced

Low-power wireless sensor networks (WSNs) design involves all aspects of research in wireless sensor networks. As energy is limited in wireless sensor networks, how to effectively manage and use energy of WSNs, and how to maximize the reduction of power consumption in WSNs and extend the lifetime of WSNs become a key problem faced by wireless sensor networks. Aimed at these problems, a low-power clustering routing algorithm based on load-balanced is proposed. The algorithm introduced an energy load factor to reduce the power consumption of WSNs. The simulation results show that the low-power routing algorithm can effectively reduce power consumption of networks and extend the lifetime of networks.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

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