FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS
In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.