scholarly journals A 1 to 32 GHz broadband multi-octave receiver for monolithic integrated vector network analyzers in SiGe technology

2018 ◽  
Vol 10 (5-6) ◽  
pp. 717-728
Author(s):  
Marco Dietz ◽  
Andreas Bauch ◽  
Klaus Aufinger ◽  
Robert Weigel ◽  
Amelie Hagelauer
Keyword(s):  
Noise Figure ◽  
Gain Control ◽  
Wide Frequency Range ◽  
Low Noise ◽  
Vector Network Analyzer ◽  
Ultra Wideband ◽  
Network Analyzer ◽  
Active Mixer ◽  
Input Matching ◽  
Better Than

AbstractA multi-octave receiver chain is presented for the use in a monolithic integrated vector network analyzer. The receiver exhibits a very wide frequency range of 1–32 GHz, where the gain meets the 3 dB-criterion. The differential receiver consists of an ultra-wideband low noise amplifier, an active mixer and an output buffer and exhibits a maximum conversion gain (CG) of 16.6 dB. The main design goal is a very flat CG over five octaves, which eases calibration of the monolithic integrated vector network analyzer. To realize variable gain functionality, without losing much input matching, an extended gain control circuit with additional feedback branch is shown. For the maximum gain level, a matching better than −10 dB is achieved between 1–28 GHz, and up to 30.5 GHz the matching is better than −8.4 dB. For both, the input matching and the gain of the LNA, the influence of the fabrication tolerances are investigated. A second gain control is implemented to improve isolation. The measured isolations between RF-to-LO and LO-to-RF are better than 30 dB and 60 dB, respectively. The LO-to-IF isolation is better than 35 dB. The noise figure of the broadband receiver is between 4.6 and 5.8 dB for 4–32 GHz and the output referred 1-dB-compression-point varies from 0.1 to 4.3 dBm from 2–32 GHz. The receiver draws a current of max. 66 mA at 3.3 V.

Design of a WiMedia/MBOA 0.13μm CMOS Front-End

2012 ◽  
Vol 198-199 ◽  
pp. 1306-1312
Author(s):  
Hong Zhang ◽  
Yuan Liang
Keyword(s):  
Noise Figure ◽  
Data Communication ◽  
Direct Conversion ◽  
Low Noise ◽  
Ultra Wideband ◽  
Third Order ◽  
Front End ◽  
Single Sideband ◽  
Noise Amplifier ◽  
Better Than

This paper addresses the design of a 3.0-8.0GHz direct-conversion receiver front-end chip for ultra-wideband (UWB) WiMedia/MBOA data communication. It comprises a partial noise cancellation broadband low-noise amplifier (LNA) and a linearity enhancement quadrature mixer. The simulation results show that the chip performance achieved the input reflection coefficient better than -11dB along the entire band and a minimum single sideband noise figure (SSB NF) of 6.57dB at IF frequency of baseband. The conversion gain ranges from 24.9dB to 29.5dB while the input third order interception point (IIP3) ranges from 1.5dBm to 8.7dBm. The chip core merely consumes 20mW from 1.2V supply.

A 5.7 mW, UWB LNA for Wireless Applications Using Noise Canceling Technique in 90 nm CMOS

Frequenz ◽  
2020 ◽  
Vol 74 (1-2) ◽  
pp. 83-93
Author(s):  
Vikram Singh ◽  
Sandeep Kumar Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Cmos Process ◽  
Second Stage ◽  
Input Matching ◽  
Noise Amplifier ◽  
Noise Canceling

AbstractA 3–12 GHz ultra-wideband (UWB) low noise amplifier (LNA) is proposed in this paper. The first stage common-gate (CG), common-source (CS) noise canceling approach is used to achieve low noise-figure (NF). CG configuration at the input stage provides wideband input-matching. The noise of CG transistor is cancelled by systematically added two parallel CS transistors, whose outputs are cascoded in second stage. In order to achieve flat power gain (S21) response, a series peaking inductor is used in the second stage. The proposed LNA is designed in 90 nm CMOS process with chip-layout area of 0.467 mm2 and in comparison to the existing LNAs, it consumes a low power of 5.7 mW from a 1 V supply. The achieved input-reflection coefficient (S11) is <−7.5 dB, output-reflection coefficient (S22) is <−7.6 dB with NF < 5.8 dB for 3–12 GHz UWB and third-order intercept point (IIP3) of −19 dBm. It achieves high and flat S21 of 20.84 ± 0.28 dB over 4.2–10 GHz, with NF ranging from 2.6–3.6 dB.

A CMOS low-noise active mixer with enhanced linearity and isolation by exploiting capacitive neutralization technique

2019 ◽  
Vol 33 (18) ◽  
pp. 1950204 ◽  
Author(s):  
Benqing Guo ◽  
Huifen Wang ◽  
Jun Chen ◽  
Mohammad Mehdi Deilamsalehi
Keyword(s):  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Frequency Range ◽  
Input Stage ◽  
Active Mixer ◽  
Input Matching ◽  
Down Conversion

In this paper, a broadband complementary metal–oxide–semiconductor (CMOS) active down-conversion mixer is presented. Specifically, a capacitor cross-coupled (CCC) transconductor serves as the input stage to reduce noise figure of the mixer while providing wideband input matching. Moreover, a capacitive neutralization technique is used to compensate the source-drain parasitic of input stage and boost loop gain of the transconductor, resulting in improved isolation and linearity. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture efficiently saves power consumption of the circuit. Implemented in the TSMC 28-nm CMOS process, post-simulations show that the proposed mixer provides a maximal conversion gain of 11.4 dB and an NF of 3.9–4.7 dB across RF input frequency range of 2–9.6 GHz. The average IIP3 of 5 dBm are obtained while the mixer core consumes 6.2 mW from a 1 V supply.

A 3.1~10.6 Ghz Ultra-Wideband SiGe Low Noise Amplifier with Current-Reused Technique

2011 ◽  
Vol 130-134 ◽  
pp. 3251-3254
Author(s):  
Kang Li ◽  
Chi Liu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chao Xian Zhu ◽  
...  
Keyword(s):  
Reflection Coefficient ◽  
Silicon Germanium ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Total Power ◽  
Input Matching ◽  
Total Power Consumption ◽  
Noise Amplifier

A 3.1 ~ 10.6 GHz Ultra-Wideband SiGe Low Noise Amplifier (LNA) is proposed. This low noise amplifier utilizes a current-reused technique to increase the gain and extend the bandwidth. We have a detailed analysis for the input matching, noise figure, gain and other features. The LNA was designed with the TSMC 0.35µm bipolar silicon-germanium (SiGe) processes. Simulation results show that the input reflection coefficient is less than-9dB, the output reflection coefficient is less than-10dB, the maximum power gain of 17 dB and the minimum noise factor (NF) of 2.35dB. The total power consumption is 6.2 mW with 2.5V power supply.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

scholarly journals A 1.5–40 GHz frequency modulated continuous wave radar receiver front-end

2021 ◽  
pp. 1-11
Author(s):  
Mantas Sakalas ◽  
Niko Joram ◽  
Frank Ellinger
Keyword(s):  
Continuous Wave ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Ultra Wideband ◽  
Front End ◽  
Wave Radar ◽  
Bicmos Technology ◽  
Circuit Components ◽  
High Band

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A Novel Reconfigurable MB-OFDM UWB LNA Using Programmable Current Reuse

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Ahmed Ragheb ◽  
Ghazal Fahmy ◽  
Iman Ashour ◽  
Abdel Hady Ammar
Keyword(s):  
Orthogonal Frequency Division Multiplexing ◽  
Cmos Technology ◽  
Low Noise ◽  
Ultra Wideband ◽  
Current Reuse ◽  
Input Matching ◽  
Common Gate ◽  
Programmable Circuit ◽  
Noise Amplifier ◽  
Mode 3

This paper presents a design of a reconfigurable low noise amplifier (LNA) for multiband orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) receivers. The proposed design is divided into three stages; the first one is a common gate (CG) topology to provide the input matching over a wideband. The second stage is a programmable circuit to control the mode of operation. The third stage is a current reuse topology to improve the gain, flatness and consume lower power. The proposed LNA is designed using 0.18 μm CMOS technology. This LNA has been designed to operate in two subbands of MB-OFDM UWB, UWB mode-1 and mode-3, as a single or concurrent mode. The simulation results exhibit the power gain up to 17.35, 18, and 11 dB for mode-1, mode-3, and concurrent mode, respectively. The NF is 3.5, 3.9, and 6.5 and the input return loss is better than −12, −13.57, and −11 dB over mode-1, mode-3, and concurrent mode, respectively. This design consumes 4 mW supplied from 1.2 V.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

Design of a Ku-band MMIC LNA with a Simple T-type Input Matching Network

2020 ◽  
Vol 29 (11) ◽  
pp. 2020006
Author(s):  
Tian Qi ◽  
Songbai He ◽  
Cheng Zhong ◽  
Zhitao Zhu
Keyword(s):  
Integrated Circuit ◽  
Return Loss ◽  
Noise Figure ◽  
Low Noise ◽  
Matching Network ◽  
Monolithic Microwave Integrated Circuit ◽  
Input Matching ◽  
Satellite Applications ◽  
Feedback Structure ◽  
Noise Amplifier

In this paper, the design of a wideband monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) fabricated in 0.13-[Formula: see text]m GaAs pHEMT process is presented. A simple T-type input matching network (IMN) and a source feedback structure are employed to achieve low noise figure (NF). The MMIC LNA, which operates across 12–18[Formula: see text]GHz, can be used for satellite applications. Experimental results show an NF around 1.5[Formula: see text]dB in 12–17.5[Formula: see text]GHz and a minimum NF of 1.21[Formula: see text]dB at 16.5[Formula: see text]GHz. In addition, a flat small-signal gain of [Formula: see text][Formula: see text]dB is achieved at 13.5–17.5[Formula: see text]GHz. The input return loss is lower than [Formula: see text] dB at 12–14.5[Formula: see text]GHz and the output return loss is lower than [Formula: see text] dB at 12–17[Formula: see text]GHz. The power consumed is lower than 0.3[Formula: see text]W and the [Formula: see text] (1-dB compression point) output power is around 13[Formula: see text]dBm.

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