High-Speed LMS Algorithm’s Design and Implementation Based on FPGA

2011 ◽  
Vol 301-303 ◽  
pp. 1157-1161
Author(s):  
Jing Jing Liang ◽  
Jing Min Gao ◽  
Wei Xin Ling
Keyword(s):  
Fixed Point ◽  
High Speed ◽  
Hardware Implementation ◽  
Adaptive Equalizer ◽  
Experimental Proof ◽  
Software Simulation ◽  
Design And Implementation ◽  
Simulation Results ◽  
Implementation Method ◽  
High Application

This Paper Proposes a Kind of High-Speed Hardware Implementation Method by the Adaptive Equalizer (LMS Equalizer) Based on MSE Criteria. this Design First Makes Full Use of FPGA Internal Hardware on Time-Multiplier (DSP48Es), and Uses the High Throughput of the Streaming Design. then Reoccupy Matlab Software Simulation and Fixed Point Design, Finally Realized ML506 Development Board in Hardware Association Simulation. Experimental Proof, both the Simulation Results Are Consistent, and it Shows that the Proposed Algorithm Is Feasibility and Efficiency, and Has a High Application Value.

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

2013 ◽  
Vol 2 (1) ◽  
pp. 15
Author(s):  
Sachin B. Jadhav ◽  
Jayamala K. Patil ◽  
Ramesh T. Patil
Keyword(s):  
Binary Tree ◽  
High Speed ◽  
Hardware Implementation ◽  
Critical Path ◽  
Partial Product ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
Multiplication Process ◽  
Major Bottleneck ◽  
Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

2017 ◽  
Vol 6 (01) ◽  
pp. 14-19
Author(s):  
Prof. Parvaneh Basaligheh
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Digital Systems ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
High Speeds ◽  
Vedic Multiplier ◽  
High Level

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM

2006 ◽  
Vol 15 (01) ◽  
pp. 129-144 ◽  
Author(s):  
SHUGANG WEI ◽  
KENSUKE SHIMIZU
Keyword(s):  
Word Length ◽  
High Speed ◽  
Large Scale ◽  
Number System ◽  
Modular Multiplication ◽  
Large Scale Integration ◽  
Modular Multiplier ◽  
Simulation Results ◽  
Implementation Method ◽  
Scale Integration

In this paper, a new three-operand modulo (2p ± 1) addition is implemented by performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. Thus, the delay time of the three-operand modular adder is independent of the word length of the operands. A modulo (2p ± 1) multiplier is constructed as a ternary tree of the three-operand modular SD adders, and the modular multiplication time is proportional to log 3 p. When a serial modular multiplier is constructed using the three-operand modular SD adder, two modular partial products can be added to the sum at the same time. Two kinds of Booth recoding methods are also proposed to reduce the partial products from p to p/2. Therefore, the performance of a parallel modular multiplier can be modified by reducing half of the modular SD adders in the adder tree. For a serial modular multiplication, two partial products are generated from two Booth recoders and added to the sum by using one three-operand modular SD adder, so that the speed of the modular multiplication is three times as fast as the speed without using the three-operand modular SD adder and the Booth recoding method. A very large-scale integration (VLSI) implementation method by VHDL is also discussed. The design and simulation results show that high-speed modular multipliers can be obtained by the algorithms presented.

Unified High-Speed EMT Equivalent and Implementation Method of MMCs With Single-Port Submodules

2019 ◽  
Vol 34 (1) ◽  
pp. 42-52 ◽  
Author(s):  
Jianzhong Xu ◽  
Yuchen Zhao ◽  
Chengyong Zhao ◽  
Hui Ding
Keyword(s):  
High Speed ◽  
Single Port ◽  
Implementation Method

scholarly journals Verification of electric steel punching simulation results using microhardness

2021 ◽  
Author(s):  
Sampsa Vili Antero Laakso ◽  
Ugur Aydin ◽  
Peter Krajnik
Keyword(s):  
Plastic Deformation ◽  
High Speed ◽  
Steel Sheet ◽  
Electrical Steel ◽  
High Speed Steel ◽  
Experimental Methods ◽  
Fem Simulations ◽  
Iron Losses ◽  
Simulation Results ◽  
Electrical Steel Sheet

AbstractOne of the most dominant manufacturing methods in the production of electromechanical devices from sheet metal is punching. In punching, the material undergoes plastic deformation and finally fracture. Punching of an electrical steel sheet causes plastic deformation on the edges of the part, which affects the magnetic properties of the material, i.e., increases iron losses in the material, which in turn has a negative effect on the performance of the electromagnetic devices in the final product. Therefore, punching-induced iron losses decrease the energy efficiency of the device. FEM simulations of punching have shown significantly increased plastic deformation on the workpiece edges with increasing tool wear. In order to identify the critical tool wear, after which the iron losses have increased beyond acceptable limits, the simulation results must be verified with experimental methods. The acceptable limits are pushed further in the standards by the International Electrotechnical Commission (IEC). The new standard (IEC TS 60034-30-2:2016) has much stricter limits regarding the energy efficiency of electromechanical machines, with an IE5 class efficiency that exceeds the previous IE4 class (IEC 60034-30-1:2014) requirements by 30%. The simulations are done using Scientific Forming Technologies Corporation Deform, a finite element software for material processing simulations. The electrical steel used is M400-50A, and the tool material is Vanadis 23, a powder-based high-speed steel. Vanadis 23 is a high alloyed powder metallurgical high-speed steel with a high abrasive wear resistance and a high compressive strength. It is suitable for cold work processing like punching. In the existing literature, FEM simulations and experimental methods have been incorporated for investigating the edge deformation properties of sheared surfaces, but there is a research gap in verifying the simulation results with the experimental methods. In this paper, FEM simulation of the punching process is verified using an electrical steel sheet from real production environment and measuring the deformation of the edges using microhardness measurements. The simulations show high plastic deformation 50 μm into the workpiece edge, a result that is shown to be in good agreement with the experimental results.

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

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