An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.

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The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.462-463.1194 ◽

2011 ◽

Vol 462-463 ◽

pp. 1194-1199

Author(s):

Zainudin Kornain ◽

Azman Jalar ◽

Rozaidi Rashid ◽

Shahrum Abdullah

Keyword(s):

Thermal Expansion ◽

Flip Chip ◽

Ball Grid Array ◽

Process Time ◽

Curing Process ◽

Curing Time ◽

Hold Temperature ◽

Flip Chip Packaging ◽

Time Cycle ◽

The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

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Development of No Flow Underfills for Lead-Free Flip Chip Applications

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology ◽

10.1115/imece2006-13420 ◽

2006 ◽

Author(s):

Kaustubh Nagarkar ◽

Tan Zhang ◽

David Esler ◽

David Simon ◽

Paul Gillespie ◽

...

Keyword(s):

Flip Chip ◽

Coefficient Of Thermal Expansion ◽

Stencil Printing ◽

Significant Research ◽

Flip Chip Packaging ◽

Chip Carrier ◽

Packaging Industry ◽

The Impact ◽

Semiconductor Packaging ◽

Underfill Material

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.

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The Effect of Underfill Fillet Geometry to Die Edge Stress for Flip Chip Packaging

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.148-149.1108 ◽

2010 ◽

Vol 148-149 ◽

pp. 1108-1111 ◽

Cited By ~ 1

Author(s):

A. Jalar ◽

Zainudin Kornain ◽

Rozaidi Rasid ◽

Saifollah Abdullah ◽

Norinsan Kamil Othman

Keyword(s):

Flip Chip ◽

Thermal Loading ◽

Ball Grid Array ◽

Parameters Optimization ◽

Dynamic Mechanical Analyzer ◽

Element Analysis ◽

Ceramic Ball ◽

Die Stress ◽

Flip Chip Packaging ◽

Edge Cracking

The possible source of die edge cracking for Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA) models were used to analyze the effect of underfill fillet geometry on interfacial stresses between die edge and the underfill fillet. The input parameters of FC-CBGA from industry was used for simulation and the properties of commercial underfill were extracted by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA). Die stress distribution for different fillet height were generated to depict variation of stress due thermal loading. The variation of tensile stress due different fillet height and width were discussed for parameters optimization.

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