Development of No Flow Underfills for Lead-Free Flip Chip Applications

2006 ◽  
Author(s):  
Kaustubh Nagarkar ◽  
Tan Zhang ◽  
David Esler ◽  
David Simon ◽  
Paul Gillespie ◽  
...  
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Stencil Printing ◽  
Significant Research ◽  
Flip Chip Packaging ◽  
Chip Carrier ◽  
Packaging Industry ◽  
The Impact ◽  
Semiconductor Packaging ◽  
Underfill Material

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.

An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

2010 ◽  
Vol 97-101 ◽  
pp. 23-27 ◽  
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Statistic Analysis ◽  
Curing Process ◽  
Ceramic Ball ◽  
Die Attach ◽  
Ball Grid Array Package ◽  
Flip Chip Packaging ◽  
The Impact

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Process Time ◽  
Curing Process ◽  
Curing Time ◽  
Hold Temperature ◽  
Flip Chip Packaging ◽  
Time Cycle ◽  
The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR

2002 ◽  
Vol 12 (02) ◽  
pp. 521-529 ◽  
Author(s):  
MIKHAIL DOROJEVETS
Keyword(s):  
Flip Chip ◽  
Clock Frequency ◽  
Single Chip ◽  
Rapid Single Flux Quantum ◽  
Flip Chip Packaging ◽  
Chip Carrier ◽  
5 Ghz ◽  
Architecture And Design ◽  
And Control ◽  
Instruction Memory

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

Study of Thermo-Mechanical Reliability of TSV for 8-Layer Stacked Multi Chip Package

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001697-001725
Author(s):  
Sung-Hoon Choa ◽  
Jin Young Choi ◽  
Cha Gyu Song ◽  
Haeng Soo Lee
Keyword(s):  
Thermal Expansion ◽  
Fatigue Life ◽  
Thermal Fatigue ◽  
Coefficient Of Thermal Expansion ◽  
Influential Factors ◽  
Design Parameters ◽  
Mechanical Reliability ◽  
Thermal Fatigue Life ◽  
The Impact ◽  
Underfill Material

Through silicon via (TSV) technology is becoming a hot topic for three dimensional integration in IC packaging industry. However, TSV technology raises several reliability concerns particularly caused by thermally induced stress. In this study, the thermo-mechanical reliability of copper TSV technology for the multi chip packaging was investigated using finite element method. For the multi chip package design, the 8-layer stacked chip packaging with TSV structure has been constructed as our test vehicle. The numerical analysis of stress/strain distribution and thermal fatigue life prediction were performed in order to study the impact of several design parameters such as via diameter, via pitch, die thickness, bonding pad geometry. The effects of various underfill materials which have different Young¡¯s modulus and coefficients of thermal expansion (CTEs) were also investigated. The DOE (design of experiment) analysis was performed to find the optimal design conditions for 8-layer multi chip package. The most influential factors for the stress reduction are TSV diameter and the coefficient of thermal expansion of underfill material. The larger via diameter and lower CTE showed the smaller stress distribution. On the other hand, thermal fatigue life increases with via diameter, and becomes maximum at via diameter of 20 um, then decrease with increasing via diameter. The presence of underfill material significantly increased the thermal fatigue life of TSV structure. The bonding pad design is also important for TSV durability. The smaller bonding pad showed less stress and higher thermal fatigue life. The characteristics of warpage for 8-layer multi chip package were also investigated.

Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design

2017 ◽  
Vol 2017 (1) ◽  
pp. 000508-000512
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Passivation Layer ◽  
Fracture Rate ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Passivation Layers ◽  
Solder Balls ◽  
Interaction Stress ◽  
Underfill Material

Abstract Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.

The Characterization of Underfill-Passivation Interface Under Monotonic and Fatigue Loading and Its Application to Flip Chip Reliability Prediction

2005 ◽  
Author(s):  
Saketh Mahalingam ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Reasonable Agreement ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Reliability Prediction ◽  
Paris Law ◽  
Joint Reliability ◽  
Electrical Interconnection ◽  
Flip Chip Packaging ◽  
Underfill Material

Flip chip packaging technology is an attractive technique to achieve mechanical and electrical interconnection between the silicon chip and the substrate. Solder joint reliability in flip chip on organic board (FCOB) is enhanced by underfill application. The failure of solder joints in a flip chip package is usually associated with underfill delamination, esp. from the chip passivation. In this work, the fracture toughness of this interface is characterized for a novel no-flow underfill material using an innovative residual stress induced decohesion (RSID) test. Numerical modeling of the chip passivation-underfill interface indicates that the delamination will not progress under monotonic loading. However, the progress of delamination occurs under repeated thermal cycling. An empirical Paris law for underfill delamination has been developed and has been applied to predict delamination in actual flip chip packages. A reasonable agreement between the two is shown.

Thermal characterization of an epoxy-based underfill material for flip chip packaging

2000 ◽  
Vol 357-358 ◽  
pp. 1-8 ◽  
Author(s):  
Yi He ◽  
Brian E Moreira ◽  
Alan Overson ◽  
Stacy H Nakamura ◽  
Christine Bider ◽  
...  
Keyword(s):  
Flip Chip ◽  
Thermal Characterization ◽  
Flip Chip Packaging ◽  
Underfill Material
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