Charge Trap Mechanism in Hybrid Nanostructured (YMnO3) Metal-Oxide-Semiconductor (MOS) Devices

2016 ◽  
Vol 42 ◽  
pp. 92-99
Author(s):  
J.H. Markna ◽  
Davit Dhruv ◽  
K.N. Rathod ◽  
Chirag Savaliya ◽  
T.M. Shiyani ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Oxide Layer ◽  
Debye Length ◽  
Anomalous Behavior ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mos Capacitor ◽  
Charge Trap ◽  
Mos Devices ◽  
A Charge

Hybrid nanostructured Metal Oxide Semiconductor (MOS) capacitor was fabricated on silicon substrates (n-type) using chemical solution deposition with YMnO3 as an oxide layer. Electrical properties of MOS capacitor have been investigated with frequency dependence capacitance-voltage (C-V) characterization. The surface morphology of deposited layer was studied using the Atomic Force Microscopy (AFM). Hysteresis in the C-V loop and change in the values of Cminimum were described by a charge trap mechanism in the multiferroic oxide layer of MOS devices. While anomalous behavior in saturation capacitance in the inversion as well as in accumulation region and a shift in threshold voltage (VT) were explained in the vicinity of frequency depended Debye length (LDebye).

Electrical and Structural Properties of Metal-Oxide-Semiconductor (MOS) Devices with Pt/Ta2O5 Gate Stacks

2011 ◽  
Vol E94-C (5) ◽  
pp. 846-849
Author(s):  
Hoon-Ki LEE ◽  
S.V. Jagadeesh CHANDRA ◽  
Kyu-Hwan SHIM ◽  
Jong-Won YOON ◽  
Chel-Jong CHOI
Keyword(s):  
Metal Oxide ◽  
Structural Properties ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Stacks ◽  
Mos Devices

Characterization of Graphene Gate Electrodes for Metal-Oxide-Semiconductor Devices

MRS Advances ◽  
2017 ◽  
Vol 2 (02) ◽  
pp. 103-108 ◽  
Author(s):  
Yanbin An ◽  
Aniruddh Shekhawat ◽  
Ashkan Behnam ◽  
Eric Pop ◽  
Ant Ural
Keyword(s):  
Metal Oxide ◽  
High Frequency ◽  
Tunneling Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Heterogeneous Integration ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Capacitance Voltage

ABSTRACT We fabricate and characterize metal-oxide-semiconductor (MOS) devices with graphene as the gate electrode, 5 or 10 nm thick silicon dioxide as the insulator, and silicon as the semiconductor substrate. We find that Fowler-Nordheim tunneling dominates the gate current for the 10 nm oxide device. We also study the temperature dependence of the tunneling current in these devices in the range 77 to 300 K and extract the effective tunneling barrier height as a function of temperature for the 10 nm oxide device. Furthermore, by performing high frequency capacitance-voltage measurements, we observe a local capacitance minimum under accumulation, particularly for the 5 nm oxide device. By fitting the data using numerical simulations based on the modified density of states of graphene in the presence of charged impurities, we show that this local minimum results from the quantum capacitance of graphene. These results provide important insights for the heterogeneous integration of graphene into conventional silicon technology.

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