Lateral 4H-SiC MOSFETs with Low On-Resistance by Using Two-Zone Double RESURF Structure

2007 ◽  
Vol 556-557 ◽  
pp. 815-818
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto

4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

2014 ◽  
Vol 778-780 ◽  
pp. 832-835 ◽  
Author(s):  
Naoki Kaji ◽  
Hiroki Niwa ◽  
Jun Suda ◽  
Tsunenobu Kimoto

Ultrahigh-voltage SiC PiN diodes with an original junction termination extension (JTE) structure and improved forward characteristics are presented. A space-modulated JTE (SM-JTE) structure was designed by device simulation, and a high breakdown voltage of 26.9 kV was achieved by using a 270 μm-thick epilayer and 1050 μm-long JTE. In addition, lifetime enhancement process via thermal oxidation was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes was remarkably reduced by lifetime enhancement process. The temperature dependence of the on-resistance was also discussed.


2018 ◽  
Vol 201 ◽  
pp. 02004
Author(s):  
Shao-Ming Yang ◽  
Gene Sheu ◽  
Tzu Chieh Lee ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
...  

High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.


2007 ◽  
Vol 556-557 ◽  
pp. 983-986
Author(s):  
Hideto Tamaso ◽  
Jiro Shinkai ◽  
Takashi Hoshino ◽  
Hitoki Tokuda ◽  
Kenichi Sawada ◽  
...  

We fabricated a multi-chip module of 4H-SiC reduced surface field (RESURF)-type lateral JFETs. A single chip consists of 4 unit devices of 2.0 mm × 0.5 mm in size, which were isolated electrically from each other. The multi-chip module consists of 8 chips mounted on an AMC substrate. The drain current and the breakdown voltage of the module are over 3 A and 771 V, respectively. The turn-on time and the turn-off time are 36ns and 166ns, respectively. The module resistance is proportional to the absolute temperature to the 1.05th power.


2000 ◽  
Vol 44 (4) ◽  
pp. 613-617 ◽  
Author(s):  
J.-I Chyi ◽  
C.-M Lee ◽  
C.-C Chuo ◽  
X.A Cao ◽  
G.T Dang ◽  
...  

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