Influence of the Oxidation Temperature and Atmosphere on the Reliability of Thick Gate Oxides on the 4H-SiC C(000-1) Face

2008 ◽  
Vol 600-603 ◽  
pp. 597-602 ◽  
Author(s):  
Michael Grieb ◽  
Dethard Peters ◽  
Anton J. Bauer ◽  
Peter Friedrichs ◽  
Heiner Ryssel
Keyword(s):  
Interface State ◽  
Interface States ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Gate Oxides ◽  
Order Of Magnitude ◽  
State Densities ◽  
Density Of Interface States

The reliability of thermal oxides grown on n-type 4H-SiC C(000-1) face wafer has been investigated. In order to examine the influence of different oxidation atmospheres and temperatures on the reliability, metal-oxide-semiconductor capacitors were manufactured and the different oxides were characterized by C-V measurements and constant-current-stress. The N2O-oxides show the smallest flat band voltage shift compared to the ideal C-V curve and so the lowest number of effective oxide charges. They reveal also the lowest density of interface states in comparison to the other oxides grown on the C(000-1) face, but it is still higher than the best oxides on the Si(000-1) face. Higher oxidation temperatures result in smaller flat band voltage shifts and lower interface state densities. Time to breakdown measurements show that the charge-to-breakdown value of 63% cumulative failure for the N2O-oxide on the C(000-1) face is more than one order of magnitude higher than the highest values measured on the Si(000-1) face. Therefore it can be concluded that a smaller density of interface states results in a higher reliability of the oxide.

Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

2013 ◽  
Vol 740-742 ◽  
pp. 691-694 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Flat Band ◽  
Mos Devices ◽  
State Densities ◽  
Mos Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011cm-2eV-1under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Low Density of Interface States in n-Type 4H-SiC MOS Capacitors Achieved by Nitrogen Implantation

2005 ◽  
Vol 483-485 ◽  
pp. 693-696 ◽  
Author(s):  
Florin Ciobanu ◽  
Gerhard Pensl ◽  
Valeri V. Afanas'ev ◽  
Adolf Schöner
Keyword(s):  
Vapour Deposition ◽  
Oxidation Process ◽  
Chemical Vapour ◽  
Interface States ◽  
Conduction Band Edge ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Nitrogen Implantation ◽  
Mos Capacitors ◽  
Density Of Interface States

A surface-near Gaussian nitrogen (N) profile is implanted into n-type 4H-SiC epilayers prior to a standard oxidation process. Depending on the depth of the oxidized layer and on the implanted N concentration, the density of interface states DIT determined in corresponding 4H-SiC MOS capacitors decreases to a minimum value of approx. 1010 cm-2eV-1 in the investigated energy range (EC-(0.1 eV to 0.6 eV)), while the flat-band voltage increases to negative values due to generated fixed positive charges. A thin surface-near layer, which is highly N-doped during the chemical vapour deposition growth, leads to a reduction of DIT only close to the conduction band edge.

New Technique for Ohmic Formation

1996 ◽  
Vol 427 ◽  
Author(s):  
S. Hara ◽  
T. Teraji ◽  
H. Okushi ◽  
K. Kajimura
Keyword(s):  
Work Function ◽  
Barrier Height ◽  
Electronic States ◽  
Surface States ◽  
Interface States ◽  
Hot Water ◽  
Flat Band ◽  
Interface Charges ◽  
The Difference ◽  
Density Of Interface States

AbstractWe propose a new systematical method to control Schottky barrier heights of metal/semiconductor interfaces by controlling the density of interface electronic states and the number of charges in the states. The density of interface states is controlled by changing the density of surface electronic states, which is controlled by surface hydrogenation and flattening the surface atomically. We apply establishing hydrogen termination techniques using a chemical solution, pH controlled buffered HF or hot water. Also, slow oxidation by oxygen gas was used to flatten resultant semiconductor surfaces. The density of interface charges is changeable by controlling a metal work function. When the density of surface states is reduced enough to unpin the Fermi level, the barrier height is determined simply by the difference between the work function of a metal φm and the flat-band semiconductor ØsFB. In such an interface with the low density of interface states, an Ohmic contact with a zero barrier height is formed when we select a metal with φm < φsFB. We have already demonstrated controlling Schottky and Ohmic properties by changing the pinning degree on silicon carbide (0001) surfaces. Further, on an atomically-flat Si(111) surface with monohydride termination, we have observed the lowering of an Al barrier height.

Electrical Properties of Au/Bi4-xLaxTi3O12 Thin Film/Si Structures and Reduction of Interface States

2005 ◽  
Vol 902 ◽  
Author(s):  
Atsushi Kohno ◽  
Hiroyuki Tomari
Keyword(s):  
Interfacial Layer ◽  
Sol Gel ◽  
Frequency Dispersion ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Flat Band ◽  
Silicon Substrates ◽  
Ft Ir ◽  
The Ideal

AbstractSub-100nm-Thick Polycrystalline Bi4-xLaxTi3O12 (BLT) thin films have been formed on silicon substrates by sol-gel and spin-coating techniques. The analysis of X-ray reflectivity for the BLT/Si structure showed that the BLT film density was slightly lower than the ideal value and the interfacial layer was formed. By Fourier transform infrared spectroscopy (FT-IR) it is confirmed that the formation of the interfacial layer was due to oxidation of Si. Clockwise hysteresis was observed in capacitance-voltage (C-V) characteristics for Au/BLT/p-Si structures at a frequency range between 1 MHz – 1 kHz. The frequency dispersion of the C-V curve was caused by a large amount of interface states at BLT/Si interface. As the film was crystallized at 550°C for 2 h the maximum interface state density was ∼3.4×1011 cm-2ev-1 at 1 kHz. Also, the negative gate-voltage shift of the C-V curve from the ideal curve and the gate-bias dependence of the flat-band voltage were observed, resulting in the presence of undesirable positive charges in the film and the electron injection to the traps near the BLT/Si interface. By post-annealing of the device at 400 °C in oxygen atmosphere the interface states (fast sates) were successfully reduced to a third of the initial value and also the positive charges were significantly diminished.

Determination of Defects Concentration from C-V and G-V Curves in a MOSFET Structure

2009 ◽  
Vol 1195 ◽  
Author(s):  
Nadine Abboud ◽  
Roland Habchi
Keyword(s):  
Exposure Time ◽  
Threshold Voltage ◽  
High Field ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Field Exposure ◽  
Gate Oxides ◽  
The Difference ◽  
Charged Defects

AbstractThe gate oxides of Si based MOSFET devices are subjected to a high field in order to induce defects in the oxide bulk and at the Si/SiO2 interface. The defects are characterized by a series of gate to source capacitance and conductance measurements. Shifts in the flat band voltage and the threshold voltage are observed and are related to the position of charged defects. The difference of the equivalent charge between the two types of defects is also determined. Conductance measurements are performed to determine the difference of interface states concentration as a function of the high field exposure time.

Electrical Characterization of High-k Dielectrics by Means of Flat-Band Voltage Transient Recording

2007 ◽  
Vol 996 ◽  
Author(s):  
Salvador Duenas ◽  
Helena Castán ◽  
Héctor García ◽  
Luis Bailón ◽  
Kaupo Kukli ◽  
...  
Keyword(s):  
Electric Fields ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Localized States ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Flat Band Voltage ◽  
High K ◽  
Mos Structures

AbstractWe have carried out a comparison between flat-band transients displayed in metal-oxide-semiconductor (MOS) structures fabricated on several atomic layer deposited (ALD) high-k dielectric films: HfO2, ZrO2, Al2O3, Ta2O5, TiO2, and Gd2O3. The gate voltage as a function of time is recorded while keeping constant the capacitance at the initial flat band condition (CFB). Since samples are in darkness, under no electric fields and no charge-injection conditions, transients must be due to charge trapping of localized states produced by electrons (holes) coming from the semiconductor by tunnelling. The process is assisted by phonons and it is therefore thermally activated. The temperature-transient amplitude relation follows an Arrhenius plot which provides the thermal activation energy of soft-optical phonons. Finally, we describe the dependencies of the flat-band voltage on the setup bias history (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) of the capacitance-voltage (C-V) characteristics of MOS structures.

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