Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

2013 ◽  
Vol 740-742 ◽  
pp. 691-694 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Flat Band ◽  
Mos Devices ◽  
State Densities ◽  
Mos Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011cm-2eV-1under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

2015 ◽  
Vol 821-823 ◽  
pp. 753-756 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Martin Rambach ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Inert Gas ◽  
Breakdown Field ◽  
Wafer Surface ◽  
Mos Devices ◽  
Uniform Current ◽  
Thin Gate Oxide ◽  
Mos Structures

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Influence of the Oxidation Temperature and Atmosphere on the Reliability of Thick Gate Oxides on the 4H-SiC C(000-1) Face

2008 ◽  
Vol 600-603 ◽  
pp. 597-602 ◽  
Author(s):  
Michael Grieb ◽  
Dethard Peters ◽  
Anton J. Bauer ◽  
Peter Friedrichs ◽  
Heiner Ryssel
Keyword(s):  
Interface State ◽  
Interface States ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Gate Oxides ◽  
Order Of Magnitude ◽  
State Densities ◽  
Density Of Interface States

The reliability of thermal oxides grown on n-type 4H-SiC C(000-1) face wafer has been investigated. In order to examine the influence of different oxidation atmospheres and temperatures on the reliability, metal-oxide-semiconductor capacitors were manufactured and the different oxides were characterized by C-V measurements and constant-current-stress. The N2O-oxides show the smallest flat band voltage shift compared to the ideal C-V curve and so the lowest number of effective oxide charges. They reveal also the lowest density of interface states in comparison to the other oxides grown on the C(000-1) face, but it is still higher than the best oxides on the Si(000-1) face. Higher oxidation temperatures result in smaller flat band voltage shifts and lower interface state densities. Time to breakdown measurements show that the charge-to-breakdown value of 63% cumulative failure for the N2O-oxide on the C(000-1) face is more than one order of magnitude higher than the highest values measured on the Si(000-1) face. Therefore it can be concluded that a smaller density of interface states results in a higher reliability of the oxide.

The Investigation of Fluorine Effects on Charge Trapping and Interface State Generation in Mos Structures

1991 ◽  
Vol 219 ◽  
Author(s):  
Dunxian D. Xie ◽  
Ta-Cheng Lin ◽  
Donald R. Young
Keyword(s):  
Charge Trapping ◽  
Interface State ◽  
Flat Band ◽  
Physical Damage ◽  
Mos Devices ◽  
Interface Charge ◽  
State Generation ◽  
Fluorinated Oxides ◽  
Donor States ◽  
Mos Structures

ABSTRACTThe bulk and interface charge trapping phenomena of fluorinated oxides have been studied by various electronic measurements. Fluorine is introduced into dry oxides by low energy (25kev) implantation followed by a 1000°C N2 ambient anneal to remove physical damage. Both the flat band and the mid gap voltage shifts of such MOS devices are measured during avalanche electron injection. We have developed techniques to separate effects due to interface state generation from bulk trapping effects. The bulk electron traps in the fluorinated oxides have a different cross section from the known water-related traps in conventional oxides. The generation of fast and slow interface states for different dosages of fluorine implantation is discussed based on Q-V and C-V measurements. The fast interface donor states, generated during avalanche injection, are charged at flat band but discharged at mid gap and beyond. An optimum dosage of fluorine implantation is found to suppress the so called turn-around effect during avalanche injection due to the formation of slow donor states. Finally, injection under high temperature (120°C-150°C) anneals out most of these donor states.

A STUDY OF THE ELECTRICAL PROPERTIES OF Al2O3 FILMS DEPOSITED ON GaAs SUBSTRATES BY SPRAY PYROLYSIS

2002 ◽  
Vol 09 (05n06) ◽  
pp. 1637-1640 ◽  
Author(s):  
J. CHAVEZ-RAMIREZ ◽  
M. AGUILAR-FRUTIS ◽  
M. GARCIA ◽  
E. MARTINEZ ◽  
O. ALVAREZ-FREGOSO ◽  
...  
Keyword(s):  
Aluminum Oxide ◽  
Spray Pyrolysis ◽  
Electric Fields ◽  
Dielectric Breakdown ◽  
Spray Pyrolysis Technique ◽  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Gaas Substrates

Electrical characteristics of high quality aluminum oxide thin films deposited by the spray pyrolysis technique on GaAs substrates are reported. The films were deposited using a spraying solution of aluminum acetylacetonate in N,N-dimethylformamide and an ultrasonic mist generator. The substrates were (100) GaAs wafers Si-doped (1018 cm -3). The substrate temperature during deposition was in the range of 300–600°C. The electrical characteristics of these films were determined by capacitance and current versus voltage measurements by the incorporation of these films into metal-oxide-semiconductor structures. The interface state density resulted in the order of 1012 1/ eV-cm 2 and the films can stand electric fields higher than 5 MV/cm, without observing a destructive dielectric breakdown. The refractive index, measured by ellipsometry at 633 nm, resulted close to 1.64. The determination of the chemical composition of the films was achieved by energy dispersive X-ray spectroscopy; it resulted close to that of stoichiometric aluminum oxide (O/Al = 1.5) when films are deposited at substrate temperatures of 300–350°C.

Effect of Interfacial Localization of Phosphorus on Electrical Properties and Reliability of 4H-SiC MOS Devices

2013 ◽  
Vol 740-742 ◽  
pp. 695-698 ◽  
Author(s):  
Tsuyoshi Akagi ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Device Properties ◽  
Phosphorus Doped ◽  
Post Deposition ◽  
Mos Device

Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO2/SiC interface were fabricated on 4H-SiC by direct POCl3treatment followed by SiO2deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

Investigation of Si/4H-SiC Hetero-Junction Growth and Electrical Properties

2009 ◽  
Vol 615-617 ◽  
pp. 443-446 ◽  
Author(s):  
Owen J. Guy ◽  
Amador Pérez-Tomás ◽  
Michael R. Jennings ◽  
Michal Lodzinski ◽  
A. Castaing ◽  
...  
Keyword(s):  
Molecular Beam ◽  
Vapour Deposition ◽  
Chemical Vapour ◽  
Physical Nature ◽  
Interface State ◽  
Electron Beam Evaporation ◽  
Layer Transfer ◽  
Mos Devices ◽  
State Densities ◽  
Scanning Electron

This paper describes the growth and characterisation of Si/SiC heterojunction structures. Heterojunction structures are of interest for low on-resistance diodes and as potential solutions to fabricating SiC MOS devices with lower interface state densities. The formation of the Si/SiC heterojunction using Chemical Vapour Deposition (CVD), Molecular Beam Epitaxy (MBE), Electron Beam Evaporation under UHV conditions (EBE-UHV) and Layer Transfer (LT) are reported. The physical nature of Si/SiC structures has been investigated using scanning electron microscopy (SEM). Results of electrical characterisation of the Si/SiC heterojunctions, are also reported. Finally, thermal oxidation of a Si / SiC heterojunction structures has been performed. The C(V) characteristics of the resulting oxides are compared to conventional thermal oxides on SiC.

Direct Observation of Dielectric Breakdown Spot in Thermal Oxides on 4H-SiC(0001) Using Conductive Atomic Force Microscopy

2010 ◽  
Vol 645-648 ◽  
pp. 821-824 ◽  
Author(s):  
Kohei Kozono ◽  
Takuji Hosoi ◽  
Yusuke Kagei ◽  
Takashi Kirino ◽  
Shuhei Mitani ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
Dielectric Breakdown ◽  
Oxide Semiconductor ◽  
Conductive Atomic Force Microscopy ◽  
Mos Capacitors ◽  
Step Bunching ◽  
Force Microscopy ◽  
Line Scan ◽  
Mos Devices ◽  
Atomic Force

The dielectric breakdown mechanism in 4H-SiC metal-oxide-semiconductor (MOS) devices was studied using conductive atomic force microscopy (C-AFM). We performed time-dependent dielectric breakdown (TDDB) measurements using a line scan mode of C-AFM, which can characterize nanoscale degradation of dielectrics. It was found that the Weibull slope () of time-to-breakdown (tBD) statistics in 7-nm-thick thermal oxides on SiC substrates was much larger for the C-AFM line scan than for the common constant voltage stress TDDB tests on MOS capacitors, suggesting the presence of some weak spots in the oxides. Superposition of simultaneously obtained C-AFM topographic and current map images of SiO2/SiC structure clearly demonstrated that most of breakdown spots were located at step bunching. These results indicate that preferential breakdown at step bunching due to local electric field concentration is the probable cause of poor gate oxide reliability of 4H-SiC MOS devices.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

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