Impact of Carrier Lifetime Enhancement Using High Temperature Oxidation on 15 kV 4H-SiC P-GTO Thyristor

2017 ◽  
Vol 897 ◽  
pp. 587-590 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Daniel J. Lichtenwalner ◽  
Edward van Brunt ◽  
Craig Capell ◽  
Michael J. O’Loughlin ◽  
...  
Keyword(s):  
High Temperature ◽  
Carrier Lifetime ◽  
Voltage Drop ◽  
Current Gain ◽  
Slight Reduction ◽  
Temperature Oxidation ◽  
Forward Voltage Drop ◽  
P Type ◽  
The Impact ◽  
Lifetime Enhancement

The impact of the lifetime enhancement process using high temperature thermal oxidation method on 4H-SiC P-GTOs was investigated. 15 kV 4H-SiC P-GTOs with 140 μm thick drift layers, with and without 1450°C lifetime enhancement oxidation (LEO) process, were compared. The LEO process increased the average carrier lifetime in p-type epi layer from 0.9 μs to 6.25 μs, and it was observed that the effectiveness of the lifetime enhancement process was very sensitive to the doping concentration. The device with the LEO process showed a significant reduction in forward voltage drop and a substantially lower holding current, as expected from the carrier lifetime measurements. However, a slight reduction in blocking capability was also observed from the devices treated with LEO process. The common emitter current gain (β) of the wide base test NPN BJT was approximately 10X higher for the wafer with LEO process.

Enhanced Forward Bias Operation of 4H-SiC PiN Diodes Using High Temperature Oxidation

2014 ◽  
Vol 1693 ◽  
Author(s):  
Craig A. Fisher ◽  
Michael R. Jennings ◽  
Yogesh K. Sharma ◽  
Dean P. Hamilton ◽  
Stephen M. Thomas ◽  
...  
Keyword(s):  
High Temperature ◽  
Thermal Oxidation ◽  
Carrier Lifetime ◽  
Voltage Drop ◽  
Forward Bias ◽  
Control Sample ◽  
Pin Diodes ◽  
Temperature Oxidation ◽  
Current Voltage ◽  
Forward Voltage Drop

ABSTRACTIn this paper, high temperature (>1400°C) thermal oxidation has been applied, for the first time, to 4H-SiC PiN diodes with thick (110 μm) drift regions, for the purpose of increasing the carrier lifetime in the semiconductor. PiN diodes were fabricated using 4H-SiC material that had undergone thermal oxidation performed at 1400°C, 1500°C and 1600°C, then were electrically characterized. Forward current-voltage (I-V) measurements showed that thermally oxidized PiN diodes exhibited considerably improved electrical characteristics, with devices oxidized at 1500°C having a forward voltage drop (VF) of 4.15 V and a differential on-resistance (Ron,diff) of 8.9 mΩ-cm2 at 100 A/cm2 and 25°C. Compared to typical control sample PiN diode characteristics, this equated to an improvement of 8% and 23% for VF and Ron,diff, respectively. From analysis of the reverse recovery characteristics, the carrier lifetime of the PiN diodes oxidized at 1500°C was found to be 1.05 μs, which was an improvement of around 30% compared to the control sample PiN diodes.

Improvement of Minority Carrier Lifetime in Thick 4H-SiC Epi-layers by Multiple Thermal Oxidations and Anneals

2013 ◽  
Vol 1538 ◽  
pp. 329-333 ◽  
Author(s):  
Lin Cheng ◽  
Michael J. O’Loughlin ◽  
Alexander V. Suvorov ◽  
Edward R. Van Brunt ◽  
Albert A. Burk ◽  
...  
Keyword(s):  
High Temperature ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Minority Carrier Lifetime ◽  
Power Devices ◽  
Oxidation Treatment ◽  
Temperature Oxidation ◽  
Oxidation Step ◽  
High Temperature Anneal ◽  
Lifetime Enhancement

ABSTRACTThis paper details the development of a technique to improve the minority carrier lifetime of 4H-SiC thick (≥ 100 μm) n-type epitaxial layers through multiple thermal oxidations. A steady improvement in lifetime is seen with each oxidation step, improving from a starting ambipolar carrier lifetime of 1.09 µs to 11.2 µs after 4 oxidation steps and a high-temperature anneal. This multiple-oxidation lifetime enhancement technique is compared to a single high-temperature oxidation step, and a carbon implantation followed by a high-temperature anneal, which are traditional ways to achieve high ambipolar lifetime in 4H-SiC n-type epilayers. The multiple oxidation treatment resulted in a high minimum carrier lifetime of 6 µs, compared to < 2 µs for other treatments. The implications of lifetime enhancement to high-voltage/high-current 4H-SiC power devices are also discussed.

Blocking Performance Improvements for 4H-SiC P-GTO Thyristors with Carrier Lifetime Enhancement Processes

2018 ◽  
Vol 924 ◽  
pp. 633-636 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Daniel J. Lichtenwalner ◽  
Michael O'Loughlin ◽  
Edward van Brunt ◽  
Craig Capell ◽  
...  
Keyword(s):  
High Temperature ◽  
High Temperature Oxidation ◽  
Carrier Lifetime ◽  
Field Region ◽  
Leakage Currents ◽  
Temperature Oxidation ◽  
Performance Improvements ◽  
Drift Layer ◽  
Lifetime Enhancement

An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2between amorphous SiO2and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VFover the 1300°C oxidized devices, without any impact on blocking characteristics.

Correlation of Fe-Rich Defect Centre and Minority Carrier Lifetime in p-Type Multicrystalline Silicon

2013 ◽  
Vol 440 ◽  
pp. 82-87 ◽  
Author(s):  
Mohammad Jahangir Alam ◽  
Mohammad Ziaur Rahman
Keyword(s):  
Carrier Lifetime ◽  
Minority Carrier ◽  
Minority Carrier Lifetime ◽  
Multicrystalline Silicon ◽  
Recombination Lifetime ◽  
Spatially Resolved ◽  
Carrier Recombination ◽  
Negative Role ◽  
P Type ◽  
The Impact

A comparative study has been made to analyze the impact of interstitial iron in minority carrier lifetime of multicrystalline silicon (mc-Si). It is shown that iron plays a negative role and is considered very detrimental for minority carrier recombination lifetime. The analytical results of this study are aligned with the spatially resolved imaging analysis of iron rich mc-Si.

10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 1025-1028 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Robert Callanan ◽  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Voltage Drop ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Collector Current ◽  
Forward Voltage ◽  
Collector Voltage ◽  
Forward Voltage Drop ◽  
Chip Size ◽  
Dc Current

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

Lifetime Enhancement of 4H-SiC PiN Diodes Using High Temperature Oxidation Treatment

2018 ◽  
Vol 924 ◽  
pp. 440-443
Author(s):  
Yeganeh Bonyadi ◽  
Peter M. Gammon ◽  
Olayiwola Alatise ◽  
Roozbeh Bonyadi ◽  
Philip A. Mawby
Keyword(s):  
High Temperature ◽  
Thermal Oxidation ◽  
Carrier Lifetime ◽  
Drift Region ◽  
Electrical Characteristics ◽  
Pin Diodes ◽  
Oxidation Treatment ◽  
Temperature Oxidation ◽  
Bipolar Devices ◽  
Minority Carriers

In this paper, the application of a high temperature thermal oxidation and annealing process to 4H-SiC PiN diodes with 35 μm thick drift regions is explored, the aim of which was to increase the carrier lifetime in the 4H-SiC. Diodes were fabricated using 4H-SiC material and underwent a thermal oxidation in dry pure O2 at 1550◦C followed by an argon anneal at the same temperature. Reverse recovery tests indicated a carrier lifetime increase of around 42% which is due to increase of excessive minority carriers in the drift region. The switching results illustrate that the use of this process is a highly effective and efficient way of enhancing the electrical characteristics of high voltage 4H-SiC bipolar devices.

On the Formation of Intrinsic Defects in 4H-SiC by High Temperature Annealing Steps

2012 ◽  
Vol 717-720 ◽  
pp. 247-250 ◽  
Author(s):  
Bernd Zippelius ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
High Temperature ◽  
Carrier Lifetime ◽  
Growth Conditions ◽  
Device Fabrication ◽  
Defect Concentration ◽  
Epitaxial Layers ◽  
High Temperature Annealing ◽  
Intrinsic Defects ◽  
Initial Defect ◽  
The Impact

In this paper the impact of high temperature annealing on the formation of intrinsic defects in 4H-SiC such as Z1/2 and EH6/7 was examined. Therefore, three epitaxial layers with various initial concentrations of the Z1/2- and EH6/7-centers (1011 – 1013 cm-3) were investigated. It turns out that depending on the initial defect concentration the high temperature annealing leads to a monotone increase of the Z1/2- and EH6/7-concentration in a temperature range from 1600 to 1750°C. For a defined temperature above these values, the resulting defect concentration is independent of the sample’s initial values. Beside the growth conditions themselves such as C/Si ratio the thermal post-growth processing has a severe impact on the carrier lifetime which must be taken into account during device fabrication.

1000 V, 30 A SiC Bipolar Junction Transistors and Integrated Darlington Pairs

2005 ◽  
Vol 483-485 ◽  
pp. 901-904 ◽  
Author(s):  
Sumi Krishnaswami ◽  
Anant K. Agarwal ◽  
Craig Capell ◽  
Jim Richmond ◽  
Sei Hyung Ryu ◽  
...  
Keyword(s):  
Room Temperature ◽  
Voltage Drop ◽  
Active Area ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Collector Current ◽  
Bipolar Junction Transistor ◽  
Forward Voltage Drop ◽  
Junction Transistor ◽  
A Current

1000 V Bipolar Junction Transistor and integrated Darlington pairs with high current gain have been developed in 4H-SiC. The 3.38 mm x 3.38 mm BJT devices with an active area of 3 mm x 3 mm showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm2, at a forward voltage drop of 2 V. A common-emitter current gain of 40 was measured on these devices. A specific on-resistance of 6.0 mW-cm2 was observed at room temperature. The onresistance increases at higher temperatures, while the current gain decreases to 30 at 275°C. In addition, an integrated Darlington pair with an active area of 3 mm x 3 mm showed a collector current of 30 A at a forward drop of 4 V at room temperature. A current gain of 2400 was measured on these devices. A BVCEO of 1000 V was measured on both of these devices.

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