Impact of Galvanic Corrosion on Metal Gate Stacks

2009 ◽  
Vol 145-146 ◽  
pp. 215-218
Author(s):  
Masayuki Wada ◽  
Sylvain Garaud ◽  
I. Ferain ◽  
Nadine Collaert ◽  
Kenichi Sano ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Galvanic Corrosion ◽  
Gate Stacks ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
Fermi Level Pinning ◽  
Gate Electrodes ◽  
High K ◽  
Work Functions

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme

2012 ◽  
Vol 187 ◽  
pp. 57-60 ◽  
Author(s):  
Guang Yaw Hwang ◽  
J.H. Liao ◽  
S.F. Tzou ◽  
Mark Lin ◽  
Autumn Yeh ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Gate Dielectrics ◽  
Semiconductor Industry ◽  
Wet Etching ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
Gate Current ◽  
Gate Electrodes ◽  
Polysilicon Gate ◽  
High K

Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.

Evaluation of Hafnium Contamination on Wafer Surfaces after the Wet Cleaning Process

2012 ◽  
Vol 195 ◽  
pp. 265-268
Author(s):  
Suguru Saito ◽  
Yoshiya Hagimoto ◽  
Hayato Iwamoto
Keyword(s):  
High Performance ◽  
Gate Dielectrics ◽  
Wafer Surface ◽  
Cleaning Process ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
Gate Electrodes ◽  
High K ◽  
Device Properties ◽  
Wafer Surfaces

High-k gate dielectrics and metal gate electrodes have become essential for emerging device technologies because they enable the continuous scaling down of devices while maintaining a high performance [. However, since they are composed of novel metallic elements that have never before been used in conventional processes, special care must be taken when handling these materials in the production line. In particular, cross-contamination that occurs due to transporting contamination via processed wafers can cause serious problems such as deterioration of device properties and yield loss [. The process of cleaning the backside and bevel of a wafer is now increasingly important for avoiding these problems. To date, there has been no detailed evaluation of contamination removal on various films performed for elements such as hafnium, which is one of the key elements in high-k/metal gate technologies. In this study, we evaluated hafnium contamination on three types of wafer surface after the cleaning process and investigated the cause of different residual amounts of hafnium contamination on the different wafers.

MOSFET AND FRONT-END PROCESS INTEGRATION: SCALING TRENDS, CHALLENGES, AND POTENTIAL SOLUTIONS THROUGH THE END OF THE ROADMAP

2002 ◽  
Vol 12 (02) ◽  
pp. 267-293 ◽  
Author(s):  
PETER M. ZEITZOFF ◽  
JAMES A. HUTCHBY ◽  
HOWARD R. HUFF
Keyword(s):  
Process Integration ◽  
Gate Dielectrics ◽  
Double Gate ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Technology Roadmap ◽  
Front End ◽  
High K ◽  
Ic Technology

The development of advanced MOSFETs for future IC technology generations is discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS). Starting from overall chip circuit requirements, MOSFET and front-end process integration technology requirements and scaling trends are discussed, as well as some of the key challenges and potential solutions. These include the use of high-k gate dielectrics, metal-gate electrodes, and perhaps the use of non-classical devices such as double-gate MOSFETs in the later stages of the ITRS.

Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
New Technology ◽  
Cmos Technology ◽  
Dielectric Surface ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Low Threshold ◽  
Work Functions ◽  
Electrical Reliability

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

On the positive channel threshold voltage of metal gate electrodes on high-permittivity gate dielectrics

2007 ◽  
Vol 102 (7) ◽  
pp. 074511 ◽  
Author(s):  
J. K. Schaeffer ◽  
D. C. Gilmer ◽  
S. Samavedam ◽  
M. Raymond ◽  
A. Haggag ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
High Permittivity ◽  
Gate Electrodes
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