Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

2009 ◽  
Vol 145-146 ◽  
pp. 215-218
Author(s):  
Masayuki Wada ◽  
Sylvain Garaud ◽  
I. Ferain ◽  
Nadine Collaert ◽  
Kenichi Sano ◽  
...  

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.


2006 ◽  
Vol 27 (3) ◽  
pp. 148-150 ◽  
Author(s):  
Chin-Lung Cheng ◽  
Kuei-Shu Chang-Liao ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang ◽  
Howard Chih-Hao Wang

2007 ◽  
Vol 84 (9-10) ◽  
pp. 2196-2200 ◽  
Author(s):  
J.K. Schaeffer ◽  
D.C. Gilmer ◽  
C. Capasso ◽  
S. Kalpat ◽  
B. Taylor ◽  
...  

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2516-2521
Author(s):  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang

2000 ◽  
Vol 611 ◽  
Author(s):  
Pushkar Ranade ◽  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
...  

ABSTRACTMolybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (∼2610°C) and low coefficient of thermal expansion (5×10−6/°C, at 20 °C) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored.


2001 ◽  
Vol 22 (5) ◽  
pp. 227-229 ◽  
Author(s):  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
P. Ranade ◽  
H. Takeuchi ◽  
K.J. Yang ◽  
...  

2019 ◽  
Vol 2 (1) ◽  
pp. 41-48
Author(s):  
Rosa María Luna-Sánchez ◽  
Ignacio González-Martínez

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