Improved Cleaning Process for Etch Residue Removal in an Advanced Copper/Low-k Device without the Use of DMAC (Dimethylacetamide)

2012 ◽  
Vol 187 ◽  
pp. 245-248
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Sang Wook Ryu ◽  
S. Naghshineeh ◽  
Yang Lee ◽  
...  

Plasma dry etching processes are commonly used to fabricate sidewalls of trenches and vias for copper / low-k dual damascene devices. Typically, some polymers remain in the trench and at the via top and sidewall. Other particulate etch residues are may remained in the bottom and on the sidewalls of vias. Generally, the particulate consists of mixtures of copper oxide with polymers. The polymers on the sidewalls and the particulate residues at the bottom of vias must be removed prior to the next process step. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the etching in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Until now, the industry has relied mainly on organic solvent containing mixtures to clean etch / ash residues from such devices. The effectiveness of available residue removers varies with the specific process and also depends on which new integration materials are used. New materials typically include Cu, TaN, low-k dielectrics and others [1-. Solvent content is thought to aid the removal of polymer residues and particulates produced during plasma dry etching processes. Therefore, in the past we have used a residue remover which contains DMAC (dimethylacetamide). But the use of DMAC is banned in microelectronic fabrication facilities in Europe because of its toxicity. Thus we wanted to find and evaluate a DMAC-free residue remover for removing polymer residues while maintaining high selectivity to the copper and ILD films.

2014 ◽  
Vol 219 ◽  
pp. 201-204 ◽  
Author(s):  
Els Kesters ◽  
Q.T. Le ◽  
D. Yu ◽  
M. Shen ◽  
S. Braun ◽  
...  

A possible way to realize a 22.5 nm 1⁄2 pitch and beyond BEOL interconnect structures within the low-kmaterial is the partial-trench via first with self-aligned double patterning (SADP) integration approach. A scheme of this BEOL integration stack with the different materials used after patterning is described in Figure 1. In BEOL processing, fluorocarbon-containing plasma is commonly used to pattern silica-based dielectric layers. During the patterning of the low-kdielectric layer, a thin layer of fluoropolymer (CFx-type residues) is intentionally deposited on the dielectric sidewalls and TiN hardmask to ensure anisotropic etching and prevent/minimize dielectric degradation. This polymer layer must be removed from the sidewall and the via bottom prior to the subsequent processing steps to achieve good adhesion and coverage of materials deposited in the etched features. The compatibility requirement is even more stringent for advanced low-kdielectrics, i.e. materials with lowerk-value and higher porosity. The post etch residue (PER) amount and properties are specific and depend on the stack structure and the plasma that is used for patterning. The low-kmaterials and hardmasks that are used in this work are respectively an organo-silicate glass (OSG) type of low-kmaterial withk= 2.4 (~20 % open porosity) and low-stress TiN. Recent results clearly showed the presence of a highly fluorinated layer deposited on the trench sidewalls during the plasma etch based on a fluorocarbon plasma [1-3]. Commodity aqueous cleaning solutions, such as diluted HF, do not efficiently remove the sidewall polymers without etching the underlying layer (lift-off). Therefore, there is a need for commercially available chemicals that can be easily tuned to deal with the different requirements. This study focuses on the use of FOTOPUR® R 2300 mixed with H2O2 for polymer residue removal selectively to other materials (presented in the stack) such as MHM, metals (Cu, W), and porous low-k dielectrics. We will show that TiN etch can be easily tuned by changing the concentration of H2O2.


2012 ◽  
Vol 187 ◽  
pp. 201-205 ◽  
Author(s):  
Nicole Ahner ◽  
Sven Zimmermann ◽  
Matthias Schaller ◽  
Stefan E. Schulz

Wet chemical plasma etch residue removal is a promising alternative to low-k dielectric degrading plasma cleaning processes. With decreasing feature dimensions the wetting behavior of the liquid on low energetic surfaces present after dielectric patterning will be an important issue in developing wet cleaning solutions. High surface energy liquids may not only be unable to wet low energetic surfaces, but can also cause nonwetting of small structures or pattern collapse. The improvement of the wetting behavior of a cleaning liquid by lowering its surface energy by the addition of surfactants is the strategy followed in this study. We show that with choosing the appropriate rinsing solution a wet chemical process using surfactant aided cleaning solutions compatible to the materials used in BEOL (porous low-k, copper, barriers) can be found. The results show a distinct improvement of the wetting behavior of the modified solutions on several low energetic solid surfaces like copper or polymers deposited during dry etching.


2000 ◽  
Vol 637 ◽  
Author(s):  
Chiharu Takahashi ◽  
Jun-Ichi Takahashi ◽  
Masaya Notomi ◽  
Itaru Yokohama

AbstractAnisortopic Si dry etching is usually carried out with chlorinated gases for electronic devices such as Si-LSIs. We had another look at Si dry etching with fluorinated gases in order to obtain an ideal air hole for two-dimensional Si photonic crystal. We simulated vertical Si etching, and showed the possibility that single crystal Si can be etched vertically with high selectivity to the etching mask using fluorinated gases. We investigated ECR etching with an SF6-CF4 mixture, and vertical Si etching was achieved at room temperature. High Si/Ni selectivity above 100 was also obtained. Two-dimensional Si photonic crystal with a photonic band gap between 1.25 and 1.51 μm was produced using SF6-CF4 ECR plasma and a thin Ni mask.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000121-000125
Author(s):  
Richard Peters ◽  
Yuanmei Cao ◽  
Kim Pollard ◽  
Don Pfettscher ◽  
Mike Phenis

The Bosch etch process is a critical process step used to create through silicon vias (TSVs) for 3D integrated circuit manufacturing. During the Bosch etch, a fluoropolymer passivation layer is formed on the sidewall of TSVs to help achieve a vertical profile and to protect the exposed dielectric materials. The fluoropolymer residue on the sidewalls in the TSVs must be removed prior to subsequent process steps. The highly fluorinated character of the fluorocarbon polymer residue makes its complete removal challenging due to characteristics such as limited solubility in solvents and slow or no reactivity with components of common cleaning or strip solutions. In this paper, the results of a study of solvents for developing formulations for removal of Bosch etch residue from TSVs are presented. The selection of components for an etch residue remover must take into consideration several key factors including removal efficiency, environmental-health-safety (EHS) guidelines, and material cost. The results demonstrate that the solvent selection has a dramatic impact on polymer removal efficiency, where poor solvent selection can lead to the formation of polymer balls inside the vias. The reported studies include cleaning results using a combination of polar solvents including protic and aprotic solvents, and amide and non-amide solvents. The cleaning performance is compared with a prediction using Hansen solubility parameters. Complete residue removal using TMAH-free and NMP-free formulations for TSV diameters down to 5 μm is demonstrated. Scanning electron microscopy, (SEM), energy-dispersive X-ray spectroscopy (EDS), and Auger electron spectroscopy (AES) were used to characterize the cleaning performance.


2016 ◽  
Vol 255 ◽  
pp. 223-226
Author(s):  
Akihisa Iwasaki ◽  
Ayumi Higuchi ◽  
Kana Komori ◽  
Masanobu Sato ◽  
Els Kesters ◽  
...  

A rapid repair process of plasma damaged SiCOH in combination with post-etch residue removal has been developed. The carbon depletion layer caused by plasma dry etching was repaired by subsequent surface modifying SAM treatment, which resulted in replenishment of carbon not only on the surface but also a few nm toward the bulk. This repairing technique provides a high-quality hydrophobic surface under conditions of low temperature and short process time. In addition, the SAM layer can be expected to act as an adhesion promotor with metal materials.


2012 ◽  
Vol 187 ◽  
pp. 241-244 ◽  
Author(s):  
Hua Cui ◽  
Martine Claes ◽  
Samuel Suhard

A novel wet cleaning formulation approach was developed with a TiN etch rate of more than 30 Å/min at room temperature and more than 100 Å/min at 50°C. The chemicals are compatible with Cu and low-k materials, and are suitable for Cu dual damascene interconnect 28 nm and smaller technology node applications. The chemicals offer a route to in situ controlled TiN pullback or even complete removal of the TiN mask during the cleaning process in single wafer tool applications. The chemicals do not contain NH4OH or TMAH and so are very user-friendly.


2014 ◽  
Vol 219 ◽  
pp. 193-196
Author(s):  
Nicole Ahner ◽  
Sven Zimmermann ◽  
Nicole Köhler ◽  
Stephan Krüger ◽  
Stefan E. Schulz

Porous ultra low constant materials (ULK) for isolation within the interconnect system of integrated circuits are a promising approach to reduce crosstalk and RC-delays due to shrinking feature sizes [1]. Due to their porosity and the integration of carbon rich species like methyl groups into the Si-O-Si backbone of currently fabricated PECVD SiCOH dielectrics those materials are highly sensible towards plasma processing, e.g. dry etching or resist stripping [2]. Metal hard mask approaches, e.g. using TiN hard masks are widely used to prevent the resist stripping plasma directly attacking the low-k material [3]. To reduce further plasma damage like carbon depletion and formation of polar silanol groups the development of less aggressive etching processes is in the focus of research and development activities. Nevertheless dry etching will attack the sidewalls and cause a material degradation. That is why repair processes, mainly based on silylation, are considered to follow the patterning step to reintegrate carbon rich species and to recover the dielectric’s properties [3]. Subsequently to dry etching and repairing the dielectric the wet chemical plasma etch residue removal process is performed. Besides material compatibility and effectiveness in residue removal the wetting behavior of the applied cleaning solutions towards the surface which has to be cleaned is crucial, especially looking on wetting issues like the incomplete wetting of very small via holes or pattern collapse. In this study we investigate in which way different silylation based repair processing regimes are affecting the wettability of the dielectric by water based cleaning solutions using contact angle based surface energy calculations.


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