Stacking of Known Good Rebuilt Wafers without TSV - Applications to Memories and SiP

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130°C +175°C, 40000g), and is fully qualified by all worldwide most important Space Agencies and for Defence applications. A technological break started in 2002 ; It consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules.The Z pitch is 100μm and the X Y size is given by the size of the larger die plus 100μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Infineon and mainly Freescale (RCP technique up to 300mm)- Stacking and gluing of KGRW 1, 2, 3…, n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation of the 3D modules This approach allows using standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to get an excellent yield. A development agreement has been signed with a semiconductors manufacturer. A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice (including a MEMS) within a cavity of 550 μm inside the 800μm SIM card. Other applications with MEMS will be presented:- “Abandoned Sensors” for Heath Monitoring of the aircraft structure developed during the European Program: “e-Cubes” ,- Gyroscope with 6 MEMS,- Micro camera for endoscopy…- Medical applications with an important development made for 3 major pacemaker manufacturers. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows stacking Good wafer at the reverse what is impossible with the wafer to wafer approach.

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Stacking of Known Good Rebuilt Wafers without TSV - Industrial Applications

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-tp36 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 001126-001174

Author(s):

Christian Val ◽

Pascal Couderc ◽

Nadia Boulay

Keyword(s):

Industrial Applications ◽

Reduction Factor ◽

Wafer Level ◽

Adhesive Film ◽

Chemical Plating ◽

Direct Laser ◽

D Modules ◽

Development Agreement ◽

Low Costs ◽

Build System

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130 °C +175 °C, 40000g), and is fully qualified by all worldwide most important Space Agencies, for Defence applications and Harsh environment. A technological break started in 2002 ; it consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules. The Z pitch is 100 μm and the X Y size is given by the size of the larger die plus 100 μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Freescale (RCP technique up to 300mm), then Infineon and Nanium (ex Infineon/Quimoda) and now about ten companies are developing this 2-D approach:- Stacking and gluing of KGRW 1, 2, 3..., n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100 μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20 μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation This approach allows to use standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to obtain an excellent yield. A development agreement has been signed with a semiconductors manufacturer. Smart card application- A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice within a cavity of 550 μm inside the 800 μm SIM card. Medical applications will be presented:- Micro modulator with 5 ASICs within a 3 mm diameter tube,- Prototypes for the major US pacemaker manufacturer (Medtronic) and one European pacemaker manufacturer (Sorin/Ela Medical). A full pacemaker module of 0,5 cm3 (16 times smaller than the standard pacemaker: 8 cm3) will be shown- Micro camera for Hard X-Ray for Philips Medical (DE). Industrial applications- Abandoned sensors for Airbus and industrial areas. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows to stack Good wafer at the reverse what is impossible with the wafer to wafer approach.

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Characterization of a photosensitive dry adhesive film for wafer level MEMS packaging

2009 International Conference on Electronic Packaging Technology & High Density Packaging ◽

10.1109/icept.2009.5270703 ◽

2009 ◽

Author(s):

Kun Zhao ◽

Changhai Wang

Keyword(s):

Wafer Level ◽

Dry Adhesive ◽

Adhesive Film ◽

Mems Packaging

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Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-tp16 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 000836-000858 ◽

Cited By ~ 1

Author(s):

Sang Hwui Lee ◽

Michael Khbeis

Keyword(s):

Low Temperature ◽

Wafer Bonding ◽

High Yield ◽

Activation Process ◽

Wafer Level ◽

3D Integration ◽

Release Process ◽

Adhesive Film ◽

Die Set ◽

Commercial Off The Shelf

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.

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Study of Three-Dimensional Small Chip Stacking Using Low Cost Wafer-Level Micro-bump/B-Stage Adhesive Film Hybrid Bonding and Via-Last TSVs

Journal of Electronic Materials ◽

10.1007/s11664-018-6701-z ◽

2018 ◽

Vol 47 (12) ◽

pp. 7544-7557 ◽

Cited By ~ 1

Author(s):

Mingjun Yao ◽

Ning Zhao ◽

Teng Wang ◽

Daquan Yu ◽

Zhiyi Xiao ◽

...

Keyword(s):

Low Cost ◽

Three Dimensional ◽

Wafer Level ◽

Adhesive Film

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Wafer-level packaging for ultra-thin glasses using hermetic room temperature welding technology

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2016dpc-tha44 ◽

2016 ◽

Vol 2016 (DPC) ◽

pp. 002203-002221 ◽

Cited By ~ 1

Author(s):

Heidi Lundén ◽

Antti Peltonen ◽

Antti Määttänen

Keyword(s):

Heat Load ◽

Adhesive Bonding ◽

Wafer Level ◽

Thin Glass ◽

Wafer Level Packaging ◽

Welding Technology ◽

Direct Laser ◽

Additive Materials ◽

Manufacturing Technologies ◽

Glass Packaging

The aim of the study was to develop a hermetic package using ultra-thin glass wafers. A novel glass welding technology, with a minimal heat load, was used to construct the encapsulations. Industry requirements of the miniaturization of the electronic components, for example in medical implants and consumer electronics and opto-electronics, challenge the conventional manufacturing technologies and package materials [1]. Low-cost glass interposers and packages have been research by GeorgiaTech at their PRC industry program. Glass packaging can offer even ten times affordable option than using silicon [2]. During the last few years, the advancements in the glass manufacturing technologies have enabled a cost effective production of the ultra-thin glass wafers and panels. Laborious glass grinding process from thick material to ultra-thin is no longer necessary since the fusion forming process can be used. Ultra-thin glass makes it possible to reduce the package size and weight [3]. Typically, glasses thickness of 300 μm or less are considered as ultra-thin material. However, even as thin as 25 μm glass is commercially available [4]. Several methods are used for glass joining including: anodic, fusion, and adhesive bonding [5]. During the recent years increasing number of laser based techniques are applied to glass packaging. Numerous studies have concentrated on frit bonding [6, 7]. Elementary study of the direct laser joining without any additive layers has been demonstrated by Miyamoto et al. [8]. Glass welding method has been further investigated in several researches [9, 10]. The package is constructed of three ultra-thin glass wafers: base and lid, thicknesses of 200 μm and spacer, thickness of 100 μm. Commercially available 6” borosilicate, D263T, wafers are used which were welded together by using novel laser welding technology. Welding is implemented on material interface without using any additive materials or coating layers. Glass surfaces are left untouched and optical quality is retained. Welding was performed on a wafer level and the single packages were cut after the final welding. Hermeticity test was performed to ensure the welding quality. Radioisotope leak test with krypton 85 was performed at Oneida Research Services. The results showed an excellent hermeticity: leak rate less than 6,0×10–12 atmcm3/s Kr-85 was achieved. Limits set in the MIL-standard are easily reached. The study proves that novel glass welding technology can be applied to wafer-level packaging with ultra-thin glasses. Technique eliminates the need of additive materials, and due to the minimal heat load bending and warping of the material can be avoided. Also, glass offers effortless visual inspection through the entire lifetime of the device.

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