Process Control for Wet Etching for Silicon Wafer Thinning

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001030-001053
Author(s):  
Laura Mauer ◽  
Herman Itzkowitz ◽  
John Taddei
Keyword(s):  
Process Control ◽  
Silicon Wafer ◽  
Etch Rate ◽  
Wet Etching ◽  
Etching Solution ◽  
Control Techniques ◽  
Cost Of Ownership ◽  
The Cost ◽  
Wet Etch ◽  
Wafer Thinning

Thin wafers have become a basic need for a wide variety of new microelectronic products. Thinner die are being required to fit into thinner packages. Wafers that have been thinned using a final wet etch process on the backside have less stress compared with standard mechanical backgrinding. Isotropic wet etching of silicon is typically done with a mixture of nitric and hydrofluoric acids along with the addition of chemicals to adjust for viscosity and surface wettability for single wafer spin processing. As the silicon is etched and incorporated in the etching solution the etch rate will decrease with time. This variation has been modeled. The focus of this paper is to compare the process control techniques for maintaining a consistent etch rate as a function of time and wafers processed. The models allow for either the time to be extended, chemicals to be replenished or a combination of these. Results will be presented including the cost of ownership for each scenario.

scholarly journals Etching of Crystalline Silicon in Thermal Environment

2011 ◽  
Vol 2 ◽  
pp. 38-42
Author(s):  
Shobha Kanta Lamichhane ◽  
Min Raj Lamsal
Keyword(s):  
Process Control ◽  
Etch Rate ◽  
Crystalline Silicon ◽  
Thermal Environment ◽  
Anisotropic Etching ◽  
Wet Etching ◽  
Control Technique ◽  
Etching Solution ◽  
Wet Etch ◽  
Process Control Technique

Thin wafer have become a basic need for a wide variety of new microelectronic products. Wafers that have been thinned using wet etch process on the backside have less stress compared with standard mechanical back grinding. Isotropic wet etching of silicon is typically done with a mixture of nitric and hydrofluoric acids. As the silicon is etched and incorporated in the etching solution the etch rate will decrease with time. This variation has been modeled. The focus of this paper is to compare the process control technique for maintaining a consistent etch rate as a function of time and wafer processed.Keywords: Isotropic and anisotropic etching; MEMS; SOI; LPCVDThe Himalayan Physics Vol.2, No.2, May, 2011Page: 38-42Uploaded Date: 1 August, 2011

Silicon Wafer Thinning to Reveal Cu TSV

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001673-001700 ◽  
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Ramey Youssef
Keyword(s):  
Silicon Wafer ◽  
Etch Rate ◽  
Cost Effective ◽  
Silicon Etching ◽  
3D Integration ◽  
Process Flow ◽  
Cost Effective Method ◽  
Etch Rates ◽  
Wet Etch ◽  
Wafer Thinning

3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes CMP and plasma have been used to complete the final thinning of the silicon. This paper will describe a simple, cost effective method to wet etch the remaining silicon to reveal the Cu TSVs. KOH is selected as the etchant since it will not attack the TSV materials and has a higher etch rate than TMAH. The development of processes with optimum etch rates and uniformity for silicon etching along with no attack of the Cu via or oxide liner and effective post cleaning to remove residual Potassium will be presented.

Monitoring of Wet Etch for Wafer Thinning and Via Reveal Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000008-000012
Author(s):  
Chuannan Bai ◽  
Eugene Shalyt ◽  
Guang Liang ◽  
Peter Bratin
Keyword(s):  
Process Control ◽  
Etch Rate ◽  
Back Side ◽  
Reaction Products ◽  
Product Characteristics ◽  
Pros And Cons ◽  
Last Stage ◽  
Silicon Vias ◽  
Wet Etch ◽  
Wafer Thinning

TSV (Through Silicon Vias) are usually formed and deposited as blind vias. As a last stage, vias are opened by thinning of the back side of the wafer. While the bulk of the silicon can be removed by both wet and dry methods, the final step of the “Via Reveal” process is predominantly performed by wet etch. Two commonly used types of etching solutions are anisotropic alkaline etch (KOH, TMAH, etc.) and isotropic etch (HF/HNO3, etc.). Etch rate, uniformity, and product characteristics strongly depend on the composition of solution: both original compounds and reaction products. This presentation describes different approaches for process control of both alkaline and acidic etch solutions using advanced spectroscopic models and potentiometry. Pros and cons of different approaches are discussed. Specific emphasis is placed on the monitoring of reaction products.

Investigation on Wet Etching 4H-SiC Damaged by Ion Implantation

2017 ◽  
Vol 897 ◽  
pp. 367-370
Author(s):  
Sophie Guillemin ◽  
Romain Esteve ◽  
Christian Heidorn ◽  
Gerald Unegg ◽  
Gerald Reinwald ◽  
...  
Keyword(s):  
Monte Carlo ◽  
Ion Implantation ◽  
Monte Carlo Simulations ◽  
Wet Etching ◽  
Etching Solution ◽  
Experimental Findings ◽  
Wet Etch ◽  
Ion Implanted

In this work investigation on wet etching of ion implanted 4H-SiC has been performed. Starting with the search for a suitable etching solution is followed by investigations on how to damage 4H-SiC in an efficient way involving different implantation species in various doses. With the help of Monte Carlo simulations a model for the experimental findings is proposed to derive the limitations for the wet etch capability.

Thermocouple Protection Tube Options for Aluminium Casthouses

2011 ◽  
Vol 693 ◽  
pp. 112-121
Author(s):  
Peter Herd ◽  
Jim Chen
Keyword(s):  
Process Control ◽  
Remote Monitoring ◽  
Temperature Monitoring ◽  
Operating Environment ◽  
Total Cost Of Ownership ◽  
Total Cost ◽  
Cost Of Ownership ◽  
Protection Tube ◽  
The Cost ◽  
Continuous Temperature

Thermocouple Protection Tubes (TCPTs) are utilised to allow continuous temperature monitoring in harsh and demanding environments for remote monitoring and process control. Choice of optimum TCPT for an application is dependent on a thorough understanding of the operating environment, characteristics of the TCPTs available and an assessment of the Total Cost of Ownership (TCO) of the different options, including the cost of the particular thermocouple being protected.

TMAH Etching of Silicon Wafer for Detector Fabrication

2014 ◽  
Vol 901 ◽  
pp. 15-20
Author(s):  
Lin Qi ◽  
Min Yu ◽  
Shao Nan Wang ◽  
Hong Zhi Liu ◽  
Bao Hua Shi ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Silicon Surface ◽  
Etch Rate ◽  
Radiation Detector ◽  
Radiation Detectors ◽  
Solution Concentration ◽  
Wet Etching ◽  
High Resistivity ◽  
Large Area ◽  
High Resistivity Silicon

Anisotropic wet etching of high resistivity silicon by TMAH for the fabrication of large area silicon radiation detectors is studied in this work. TMAH is widely applied in microelectronics and micromechanical fabrication etching low resistivity silicon, whereas the etching of high resistivity silicon was seldom studied by the industry. This work focused on the research of TMAH etching of high resistivity lager area silicon wafer aiming at its application in silicon radiation detector fabrication. We investigated the etching properties of TMAH of 4 inch (111) silicon wafers. Various parameters combinations were explored, such as TMAH solution concentration of 25wt%, 15wt% and 5wt%, and temperature of 95 °C, 90 °C and 85 °C. Etch rate, etch uniformity and silicon surface roughness were observed.

Optimization of Concentration and Temperature of KOH Etchant on Micromachining Process

2010 ◽  
Author(s):  
Mohsen Shayan ◽  
Behrooz Arezoo ◽  
Ali Amani
Keyword(s):  
Crystal Orientation ◽  
Etch Rate ◽  
Wet Etching ◽  
Etching Process ◽  
Structure Investigation ◽  
Optimal Amount ◽  
Etch Rates ◽  
Wet Etch

Due to vast application of silicon wet etching in Micromachining and MEMS structure, investigation about parameters that have more influence on wet etch rate is indispensable. Wet etch rate is dependent to several factor such as temperature, etchant concentration and crystal orientation. Because of temperature and concentration are more controllable therefore the etch rates R{hkl} depend mainly on concentration and temperature of the etchant. Understanding the relation between this parameters and wet etch rate can assist us in order to control and optimization of micromachining process. This paper present a relation between etchant concentration and temperature and wet etch rate on (100) plane, and then identify the etchant concentration in a certain range of temperature as the wet etch rate be in optimal amount. With optimization the etch rate of wafer (100), necessary time for etching process reduces and this reduction of time can lead to reduction of undercutting at convex and concave corners.

scholarly journals Infinite Selectivity of Wet SiO2 Etching in Respect to Al

Micromachines ◽  
2020 ◽  
Vol 11 (4) ◽  
pp. 365
Author(s):  
Imrich Gablech ◽  
Jan Brodský ◽  
Jan Pekárek ◽  
Pavel Neužil
Keyword(s):  
Elevated Temperature ◽  
Sheet Resistance ◽  
Etch Rate ◽  
Microelectromechanical Systems ◽  
Sacrificial Layer ◽  
Wet Etching ◽  
Water Bath ◽  
Fume Hood ◽  
Etching Solution ◽  
Unconventional Method

We propose and demonstrate an unconventional method suitable for releasing microelectromechanical systems devices containing an Al layer by wet etching using SiO2 as a sacrificial layer. We used 48% HF solution in combination with 20% oleum to keep the HF solution water-free and thus to prevent attack of the Al layer, achieving an outstanding etch rate of thermally grown SiO2 of ≈1 µm·min−1. We also verified that this etching solution only minimally affected the Al layer, as the chip immersion for ≈9 min increased the Al layer sheet resistance by only ≈7.6%. The proposed etching method was performed in an ordinary fume hood in a polytetrafluorethylene beaker at elevated temperature of ≈70 °C using water bath on a hotplate. It allowed removal of the SiO2 sacrificial layer in the presence of Al without the necessity of handling highly toxic HF gas.

A Review of Wet Etch Formulas for Silicon Semiconductor Failure Analysis

1996 ◽  
Author(s):  
T.W. Lee
Keyword(s):  
Failure Analysis ◽  
Literature Search ◽  
Wet Etching ◽  
Second Step ◽  
Environmental Concerns ◽  
Acid System ◽  
Graphical Data ◽  
Selective Etch ◽  
Chromium Compounds ◽  
Wet Etch

Abstract WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

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