Ultra-Thin and High-Density Packaging Using Both Sides Flip Chip Technology

2003 ◽  
Author(s):  
Kazuto Nishida ◽  
Kazumichi Shimizu ◽  
Michiro Yoshino ◽  
Hideo Koguchi ◽  
Nipon Taweejun
Keyword(s):  
Cross Section ◽  
Flip Chip ◽  
High Capacity ◽  
High Density ◽  
Thickness Direction ◽  
The Finite Element Method ◽  
Memory Card ◽  
Chip Technology ◽  
Chip Size ◽  
High Density Packaging

We have developed a high-density packaging technology by using a thin IC and a thin substrate and bonding it by new flip chip technology. Numerical analysis with the finite element method (FEM) as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided CSP and both-sided CSP on the thickness of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively. Moreover, a both-sided flip chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional chip-size package (CSP).

Reliability Evaluation of CSP Using New Flip-Chip Bonding Technology: Both-Sided CSP and Single-Sided CSP

2002 ◽  
Author(s):  
Hideo Koguchi ◽  
Nipon Taweejun ◽  
Kazuto Nishida ◽  
Chie Sasaki
Keyword(s):  
Finite Element Method ◽  
Cross Section ◽  
Flip Chip ◽  
High Reliability ◽  
Reliability Evaluation ◽  
Thickness Direction ◽  
Material Parameters ◽  
Conductive Film ◽  
Chip Size ◽  
Bonding Technology

Chip-size packaging (CSP) attracts largely attentions due to its lighter, thinner and smaller size. In this study, the deformations and the stresses in the CSP fabricated by non-conductive film stud-bump direct interconnection (NSD) were analyzed. The reliability evaluation of single-sided CSP and both-sided CSP were investigated for heat cycles. The material parameters, i.e. stresses, strains and deformations, for achieving a high reliability of CSP were investigated using a finite element method and experiment. The dependency of the life in single-sided CSP and both-sided CSP on the thicknesses of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively.

Reliability Prediction of Area Array Solder Joints

2003 ◽  
Vol 125 (4) ◽  
pp. 562-568 ◽  
Author(s):  
Rainer Dudek ◽  
Ralf Do¨ring ◽  
Bernd Michel
Keyword(s):  
Geometric Modeling ◽  
Flip Chip ◽  
Failure Criteria ◽  
Temperature Fields ◽  
The Finite Element Method ◽  
Chip Technology ◽  
Array Technology ◽  
Chip Scale Package ◽  
Solder Balls

Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.

The Reliability Study of a High density Multi Chip Packaging with Folding Flexible Substrate

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001846-001969
Author(s):  
Yin Wen ◽  
Bo Zhang ◽  
Yuan Lu ◽  
Liao Anmou ◽  
Du Tianmin ◽  
...  
Keyword(s):  
Cross Section ◽  
Flip Chip ◽  
Flexible Substrate ◽  
Open Circuit ◽  
High Density ◽  
Core Material ◽  
Test Results ◽  
Electrical Measurements ◽  
High Frequency Signal ◽  
Significant Change

In this century, the IC packaging technology continues to make progress at astounding rate to meet the increasing requirements in many fields[1]. High density packaging is normally achieved by using various chip and/or package staking. Due to itsunique bending characteristics, flex substrate has become an ideal candidate for high density 3D packaging, especially applied for the packaging of medical products[2,3]. In this paper, we focus on the process development details of a flexible package, and investigate the main reliability problems through a series of reliability tests. There were three chips in the 3D flexible packaging structure used in our experiments. The center chip had a larger size of 5.95à —4.35mm2, while the edge ones were smaller and had the same size of 1.95à —1.95mm2. The thickness of all the three chips was the same, 200ÃŽ ¼m. All the chips had daisy chain testing structure. The ball diameter and pitch of the bumps were 250ÃŽ ¼m and 400ÃŽ ¼m, respectively. The substrate was a double-layer non-gel flexible substrate, which had polyimide as the core material (dielectric constantâ ‰ ˆ4). The substrate had a dimension of 16.9mmà —5.5mm2, and a total thickness of 80ÃŽ ¼m. Differential transmission line and DC test pads were designed in the testing circuit for high frequency signal and DC electric test. The dimension of the 3D package after folding was about 6à —6.6à —1.3mm3. The assembly process flow is as follows: All the chips were connected to a flexible substrate by using flip-chip bonding process. After underfilling was applied and cured, the two edge chips were folded and stacked onto the center chip. Then encapsulation and BGA ball dropping were followed. By flexible folding and chip stacking, the overall package size was reduced. We chose an epoxy based material as underfilling and encapsulation. X-ray check and c-scan test showed that the encapsulation had no voids in most samples. Autoclave (RH 95%, 125Ã’ °C, 96 hours) and multireflow (260â „ ƒ for 5 times) test were designed to assess the flexible structure and check the package reliability. Electrical measurements were performed to monitor and check the REL output. Some of the important electrical test results are summarized below: (1) After the multireflow test, some of the 2D unfolding samples showed open circuit in DC test, especially around the vicinity of the larger chip in the center. The DC test results of 3D samples showed no significant change after multireflow, while cross-section image showed no delamination in these area. (2) After the autoclave test, open circuit could be observed in most 2D unfolding samples near the region of the larger chip in the center, while open circuit could be seen in some smaller chip region too. For the other good parts, resistance showed an increase of 150–200% than before. The DC test results of 3D samples showed no significant change after autoclave, and the cross-section image showed no delamination in these area. (3) It could be presumed that the center region of the large chip was the weakest link of this package. 3D folding and encapsulation had reinforcement action on the flexible substrate.

Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002272-002313
Author(s):  
Brian J. Lewis ◽  
D. F. Baldwin ◽  
P. N. Houston ◽  
B. Smith ◽  
P. Kwok ◽  
...  
Keyword(s):  
Flip Chip ◽  
Reliability Assessment ◽  
High Density ◽  
Chip Technology ◽  
Fine Pitch ◽  
Characterization Study ◽  
Alternative Materials ◽  
Full Analysis ◽  
Silicon Vias ◽  
Silicon Based

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements. The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

Sign in / Sign up

Export Citation Format

Share Document