A Study of Defects in High Reliability Die Sort Applications

For high-reliability microelectronics with uses in aerospace, defense, automotive, and medical applications, in-line visual inspection during the die sort process allows for a higher quality and more robust process for generating known-good-die. The visual inspection serves three primary functions: verifying unique device characteristics (such as bumps, MEMS structures, waveguides, etc.), verifying the device is free from singulation defects, and verifying the die sort process induces no device damage. Performing a visual inspection of the die top surface and one edge during the pick and place process allowed qualification of a non-surface contact edge grip approach for sensitive surface MEMS and optoelectronic parts. Die 100 microns thick or less were also inspected to ensure no cracking during the die pick process. For continual process reliability improvement and optimization, the inspection results must be captured and logged along with incoming product details including the wafer ID, electrical test results, and chip ID. This logged information is then traceable to the die position in the output medium. As new device manufacturing technology is implemented, this screening for process-induced defects is required for a robust manufacturing process.

Designing Software Configurable Chips and SIPs using Chiplets and zGlue

zGlue Smart Fabric, an active silicon interposer, enables rapid development of Systems in Package (SiPs) and Chips using chiplet stacking in a modular style and software programmability. zGlue Smart Fabric works with off-the-shelf chiplets in known good die and wafer level chip scale packages format without dictating a footprint constraint on chiplets. This is achieved by making a fine pitch copper pillar micro-bump array on the surface that can conform to the chiplet ball map using a programable connectivity and power array built into zGlue's fabric. Connection to RF and sensitive analog signals are handled in RDL. Programmability of zGlue bumps also enable some repair and reconfigurability after manufacturing. The design process with zGlue includes usage of a cloud-based software design tool called ChipBuilder. This tool performs most conventional SiP design functions but more importantly it is used for creating soft and hard routes among IOs. ChipBuilder starts with a data representation of zGlue's Smart Fabric. A growing library of chiplet data has been encoded into the tool and is made available to the users of ChipBuilder via the cloud. Users select chiplets, enter design, perform IO planning, and route the design. With this modular IC design style, zGlue can handle high mix devices that are expected with the growth of connected smart devices everywhere.

A Wide I/O Memory-on-Logic Product Prototype Enabled by Through-Silicon Stacking Technology

We report on a 28nm product prototype test vehicle assembled back-to-face with a 4Gb 3× nm Wide I/O DRAM chip using Through Si Stacking (TSS) technology. The high bandwidth interface of the digital chip to the wide I/O memory chip is enabled by ∼1200 μ-bump joints with pitch as small as 40μm allowing for wide memory bandwidth. With appropriate chip floor-planning, we demonstrate the mitigation of any impact to digital circuit performance and yield from TSS and the possibility to re-use 2D circuit IP in a 3D product with minimal die size growth. Our 3DIC assembly process allows for a compact form-factor package with <1mm thickness. As part of an integrated product solution, we include a test methodology with test stages distributed throughout the integration flow which allow for selection of known-good die to maximize assembly yield.

Scalable Microsprings for Integrated Test and Packaging

Lithographically defined spring electrical contacts have many applications for next generation electronics test and packaging. The springs can lower the cost of multi-chip modules because their rework ability addresses the known-good-die problem. Lower height chip stacking for mobile electronics markets is enabled because a sliding spring can have a much shorter profile than solder. Larger die can be directly bonded to the board because the compliance absorbs thermal expansion mismatches between substrates. Significant stress isolation is possible, which is important for mechanically sensitive die such as MEMS and low K die. Very high density is possible, as 6 (am pitch has been demonstrated. Fabrication is scalable and assembly is low temperature. This paper reviews our prototype demonstrations for these applications as well as relevant reliability data and contact studies.

3D-TSV Test Options and Process Compatibility

3D-TSV stacking with non-reworkable bonding processes implies known-good die screening with high test coverage to be economical.Depending upon the stack architecture, the need to contact TSVs directly or TSV bonding pads during wafer test ranges from minimal to mandatory. An example of minimal need to contact is a low-power logic or memory chip powered and tested through a small number of test pads for scan chains or built-in self-test (BIST) signals. Examples of mandatory TSV pad contact during wafer test include power delivery pins (up to thousands), analog or RF I/Os, stacked logic functions, or more complex requirements.With appropriate design, test throughput (and therefore test cost) can dramatically benefit from contacting the many more I/Os available at the TSVs or TSV pads, just as the speed of the stack benefits from the many more I/Os when in mission mode.Probes and probing processes that touch TSVs and thin pads with minimal forces and pad marking are described herein. Feasibility of tip forces ~1 gram or less and very low pad damage are demonstrated at 40 micron array pitch. The lithographically printed probe structures are scalable to even smaller pitches, and fabrication costs scale by probe area, not by pincount.The degree of pad marking from probe tips depends on pad material choices. A non-oxidizing metal surface, such as ENIG, requires <0.1 gm for good contact, thus disturbing the surface so little that marks are difficult to detect. By contrast, a Sn surface requires ~1 gm for low and consistent contact resistance. Probe contacting at TSV pitches is practical with evolutions of existing probe technology, and enables test strategies which probe some or all of the TSV pads, whether on the face or back of the wafer.