Enabling Resist Processing Technologies for Advanced Packaging

The increasing adoption of advanced wafer-level packaging (WLP) technologies and high density interposer concepts clearly reflect the permanent need for form factor reduction, smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the integration of TSVs also significant challenges have to be overcome. One of the greatest challenges for present and even more for upcoming TSV design strategies still remains the processing of photoresist and other functional polymers at and within TSV geometries. To this day, it is still very difficult to achieve a conformal polymer coating in deep cavities, along steep side walls and especially within the extreme aspect ratios of TSV. Mainly this is due to the fact that standard surface coating methods such as spin coating were just not developed to meet the requirements posed by these high aspect ratio microstructures. New and innovative approaches are needed to meet these new challenges. Spray coating is one of the most promising technologies to overcome current barriers. However, even most of the available spray deposition equipment is facing its limits with steadily decreasing via diameters and increasing aspect ratios on the other hand. Successively, the multitude of these challenging technological developments in the 3D-IC and wafer-level packaging area has created the demand for innovative manufacturing approaches, new equipment and related tools. Herein we present our new EVG ®NanoSprayTM coating technology with unique capabilities to overcome the present limits of conformal resist coating over extreme topography. We demonstrate one particularly promising application for conformal polymer coatings; as an annular lining at the interface between the conducting metal filling in the TSV and the silicon wafer. The intrinsic properties of the polymer allow a TSV design solution that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between the silicon substrate and the interfacing metal. Consequently, this new type of polymer buffered TSV interconnect design promises to significantly reduce thermal stress-induced TSV delamination as one of the dominant failure modes for 3-D interconnects. We further demonstrate the application of EVG ®NanoSprayTM as enabling coating technology for llithographic processing of conformal coated TSVs. The patterning of thin photoresist layers at the bottom of vias and along the steep sidewalls of deep cavities allows for more degrees of freedom in electrical contact formation. The presented EVG ®NanoSprayTM coating technology opens new dimensions in advanced wafer level packaging and provokes reconsidering prevailing limitations in interconnect design.