Material and Process Developments for Robust and High Reliability Glass Wafers for 2.5D Packaging

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001364-001377
Author(s):  
Roupen Keusseyan ◽  
Tim Mobley
Keyword(s):  
Borosilicate Glass ◽  
High Speed ◽  
High Reliability ◽  
Electrical Performance ◽  
Next Generation ◽  
Wafer Level ◽  
Hole Formation ◽  
Heterogeneous Devices ◽  
Primary Key ◽  
Through Hole

Borosilicate glass based wafer technologies are being developed for next generation high speed electronic, telecom and biotech systems; that integrate heterogeneous devices in a single package for improved electrical performance. The primary key to success is to have a well understood via through the glass that can be used as a core to build wafer level packages from. The present paper will discuss developments in through hole formation technology and via metallization materials and processes. Through hole formation in borosilicate glass with corresponding wall morphology and chemistry play important roles in building robust vias through the glass. These hole characteristics and their dependence on performance, defects at the wafer level and key developments that have been achieved to overcome them will be discussed in detail.

Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

Coreless Substrate Design, Assembly and Reliability for High Speed Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001486-001513
Author(s):  
Jon Aday ◽  
Nozad Karim ◽  
Mike Devita ◽  
Steven Lee
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Core Layer ◽  
Power Delivery ◽  
Advanced Materials ◽  
Band Width ◽  
Electrical Performance ◽  
Next Generation ◽  
Reliability Data ◽  
The Core

There are 2 primary drivers for advanced substrate technologies to support the next generation of products. One driver is silicon designs which are shifting to 20–40 GBit applications. The band width of these products are requiring advanced materials, and designs which use much thinner cores making routing and manufacturing of these packages easier. The second driver is the move more advanced silicon nodes which also drives the importance for much better power delivery. Coreless substrates enable both of these applications by eliminating the core layer which enables much finner via pitchs to route signals and power/gnd planes. The thinness also reduces the bandwidth used up by the substrate which also enables better electrical performance. This paper will focus on the electrical drivers including simulation to support the structure, flip chip assembly of the package as well as the reliability data associated with the assembly.

Next generation thin film polymers for WLP applications and their mechanical and electrical characterization

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000656-000678
Author(s):  
Markus Woehrmann ◽  
M. Toepper ◽  
H. Walter ◽  
K.-D. Lang
Keyword(s):  
Thin Film ◽  
Material Property ◽  
Polymer Materials ◽  
Electrical Performance ◽  
Material System ◽  
Next Generation ◽  
Wafer Level ◽  
Aging Effects ◽  
Special Equipment

Thin film polymers, like PI, PBO and BCB are used in every wafer level packaging device. The improvement of the reliability of wafer-level packages and chip I/Os consider the choice of the polymer, which is used as dielectric on the chip, as a minor point. Because the production lines are normally fixed on one polymer and the high investments to evaluate the processing of an alternative polymer formulation in combination with costly reliability test seems to be not attractive till today. But the increased demands of advanced WLP and 3-D-Integration, which includes thin chips, chips stacking and higher routing densities, leads to reaching the limits of the common used material system combinations. The demand of better polymer films becomes evident by the fact that dozens of “next generation polymers” have entered the marked in the last years, which are tailored to get higher mechanical toughness and electrical performance aside of a nearly unchanged resolution capacity. The challenge for new polymer formulation is the evaluation of the processing and the generation of a reliable material property data base, which set the basics for any benchmarking to the already used polymer materials. The processing evaluation is done typically by the material supplier or the fab himself, where no special equipment is needed. The material property generation is a quite more complex topic because you need special equipment and partly the material need to be free standing without any substrate. This is also a handling issue, if we talk about thin films in the range of 5 to 20μm. This paper presents the reliable thin film polymer properties characterization of mechanical and electrical values. The measurements of the mechanical properties include the estimation of parameters like young's modulus, tensile strength, elongation at break, coefficient of thermal expansion, stress and time-temperature related effects. The evident topic of warpage related impacts by “new generation polymers” will be presented and discussed. Measurement structures on wafer-level are developed for the estimation of the electrical parameters, which allows a high accuracy and a device relevant value estimation. Parameters like break down voltage, leakage current, dielectric constant, loss factor are measured related to frequencies by MIM and resonator structures. We demonstrate with analyzing of the time-dependent dielectric breakdown (TDDB) of thin film polymers that there is an exponential linkage between field strength and the time till the breakthrough occurs. The mechanical and electrical properties were also investigated related to aging effects, when the application is running on elevated temperature. We examine a degradation of the mechanical and electrical performance, which should be taken into account for the mechanical system reliability and also for impedance controlled HF-application. This paper present advanced material characterization of thin film polymers which gives a guideline for the decision of the polymer related to the demands of the application.

The Package Becomes the System

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-36
Author(s):  
Bruce J. Barbara
Keyword(s):  
High Reliability ◽  
Electrical Performance ◽  
Entire System ◽  
Single System ◽  
Wafer Level ◽  
Electromechanical Systems ◽  
Thermal Structures ◽  
On Chip ◽  
3D Stacking ◽  
System Miniaturization

The benefits of system miniaturization lower-cost, higher electrical performance and better thermal mechanical reliability, than the current approach of discrete component packaging have been discussed at length. Several technologies have been used to address these benefits. SOC, SiP, Fan-In and Fan Out and wafer level packages. Recently there has been much discussion about Fan Out Wafer Level packaging (FOWLP) to integrate the entire system in package. However, actual implementations fall short of a complete system in a package in that only few of the chips and some passives are currently integrated into the FOWLP. But what about the rest of the system? A true system also requires additional components not traditionally considered integrate-able into a package. These include antennas, batteries, thermal structures, RF, Optical, micro-electromechanical systems (MEMs), and micro sensor functions. The current FOWLP package technology as discussed by the media falls short of this type of system integration due to limitations in the number of chips that can be integrated and the lack of sufficient interconnect layers to support these functions in a system. 3D stacking has also been employed to improve the SiP by adding memory components. These implementations are limited to stacking of identical chips with through hole silicon vias (TSV) located remotely from any circuitry. Aurora Semiconductor will introduce a packaging technology where the package becomes the system. We call this technology 4DHSiP™ or 4D Heterogeneous System in package. 4DHSiP™ is a system miniaturization technology in contrast to system on chip (SOC) at the integrated circuit level and system in package stacked ICs and packages (SIP) at the module level. 4DHSiP™ is considered an inclusive system technology in which, SIP, thermal structures and batteries are considered as substantive technologies. 3D stacking is no longer limited by the location of the TSV within the stacked components. Heterogeneous multi-chip sub module layers can be stacked to accommodate additional system components. These layers, when interconnected, form the entire system. By stacking sub module layers, specific component types can be located on the top most layer as needed by specific function (e.g. Bio functions, Optical functions, Antennas). An example of this type of module stacking used to create an optical based system will be shown.4DHSiP™ is a new, emerging system concept where the device, package, and system board are miniaturized into a single system package including all the needed system functions. Such a single system package with multiple heterogeneous ICs provides all the system functions by co-design and fabrication of digital, radiofrequency (RF), optical, micro-electromechanical systems (MEMS) in either the IC or the system package. 4DHSiP™ combines the best on chip and off chip integration technologies to develop ultra-miniaturized, high-performance, multifunctional products. A significant benefit of this miniaturization is the elimination of multiple sockets and connectors currently used to connect sub-systems together. This ultra-miniaturization of multiple to mega functions, ultrahigh performance, low cost and high reliability will be the way systems are designed in the future to achieve More than Moore.

Low Temperature Curable PI/PBO for Advanced Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15 ◽  
Author(s):  
Daisaku Matsukawa ◽  
Tadamitsu Nakamura ◽  
Tetsuya Enomoto ◽  
Noriyuki Yamazaki ◽  
Masayuki Ohe ◽  
...  
Keyword(s):  
Low Temperature ◽  
Chemical Resistance ◽  
High Reliability ◽  
Dielectric Materials ◽  
The Novel ◽  
Next Generation ◽  
Wafer Level ◽  
High Chemical ◽  
High Chemical Resistance ◽  
Advanced Packaging

Photo-definable polyimides (PI) and polybenzoxazoles (PBO) have been widely used as dielectrics for re-distribution layers in wafer level chip size packages (WL-CSP). These materials can simplify the manufacturing process and ensure high reliability owing to their good mechanical properties and high thermal stability. For next generation electronic components fabricated by utilizing advanced packaging technologies such as 3D-stacking using TSV, package-on-package, fan-out WL-CSP etc., the most important requirements for dielectric materials are high lithographic performance, high adhesion to Cu RDL, high chemical resistance and low temperature curability. In this paper, we will report on our novel low temperature (<200C) curable PBO and PI. A novel alkaline positive tone PBO was developed by re-designing key components of the formulation to enhance lithographic performance, Cu adhesion and chemical resistance. It was found that the new PBO material showed higher lithographic performance than conventional PBOs due to its high dissolution contrast and which resulted in a resolution of 2micron (L/S) with a 7μm cured thickness and 3micron (L/S) with a 15micron cured thickness, respectively. This material also produced strong Cu adhesion and high chemical resistance at curing temperatures <200C with no delamination from the Cu RDL being observed after a 168hr Pressure Cooker Test (PCT). Furthermore, the new formulation showed high TCT resistance due to its high elongation below 0C. In addition, a novel solvent negative tone PI was also developed by incorporating a cross-linker to accelerate low temperature curability as well a photo-initiator to improve lithographic properties. As a result, the novel PI when cured at 175C for 1hr showed high Cu adhesion after 168hr PCT as well as high film properties. The new PI also showed excellent lithographic properties with a resolution of 6micron (L/S). Furthermore, the low temperature curable PI and PBO materials were used as dielectrics to fabricate WL-CSPs for both chip and board level reliability testing. The test results indicated that both the novel PBO and PI showed excellent reliability after thermal cycling (TCT) due to the significant improvements made to Cu adhesion and chemical resistance. These materials are expected to be promising for next generation WLP applications. Details are described in the presentation.

Anti-Counterfeit, Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

2013 ◽  
Vol 2013 (1) ◽  
pp. 000158-000165
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
How Lin
Keyword(s):  
High Speed ◽  
High Reliability ◽  
Electronic Devices ◽  
Implantable Devices ◽  
High Density ◽  
Electrical Performance ◽  
Recent Developments ◽  
Speed Performance ◽  
Advanced Packaging ◽  
Silicone Coatings

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. This paper discusses the development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for miniaturized electronic devices. In particular, recent developments in high density interconnect (HDI) substrate technology are highlighted. System-in-Package (SiP), embedded passives, stacked packages, and flex substrates are utilized to achieve significant reduction in size, weight, and power (SWaP) consumption in electronic devices. The paper also describes a novel approach for the fabrication of silicone-coated flexible substrates to provide biocompatibility for implantable devices. In particular, we highlight recent developments on silicone coatings on high density, miniaturized polyimide-based flexible electronics. A variety of high density circuits ranging from 11 microns lines/space to 25 microns lines/spaces were processed on polyimide flex substrates and subsequently coated with biocompatible silicone coatings. The electrical performance of silicone coated batteries was characterized by voltage measurements. The final structure enhances the stretching capability. Fabrication of advanced medical substrates incorporating technologies for parts authentication (anticounterfeit measures) such as embedded signature circuits and use of nano or micro materials as signatures are discussed. In some instances, these measures do not add cost to package fabrication.

High Reliability Fine Pitch WLCSP for High Pin Count Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001894-001907
Author(s):  
David Lawhead ◽  
Ronnie Yazzie ◽  
Tony Curtis ◽  
Guy Burgess ◽  
Ted Tessier
Keyword(s):  
Silver Content ◽  
High Reliability ◽  
Electrical Performance ◽  
Thermal Testing ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Industry Standard ◽  
Fine Pitch ◽  
Board Level ◽  
Board Level Reliability

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements. This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.

Acetylene-Terminated Polyimide Composites for Advanced Electronic Packaging Applications

1989 ◽  
Vol 154 ◽  
Author(s):  
A. Mahammad Ibrahim
Keyword(s):  
Electronic Packaging ◽  
High Speed ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
High Reliability ◽  
Circuit Board ◽  
Electrical Performance ◽  
Surface Mount ◽  
Plated Through Hole ◽  
Polyimide Composites

AbstractSurface mount technology (SMT) is an electronic packaging technology wherein the leads of electronic components are soldered directly to metallized pads on the surface of a printed circuit board (PCB). The SMT with leadless ceramic chip carriers (LCCCs) is used to design, fabricate, and assemble affordable, high-speed, high-density electronic modules with reduced size and weight and improved electrical performance. In surface mount devices, the LCCCs are soldered directly onto the fabric composite PCB substrate. New high-performance composite substrate materials must be developed to take full advantage of SMT. Fabricating a PCB that will perform reliably throughout its intended life is also an increasingly important requirement, especially if the goal is to satisfy the high reliability required in military applications. Consequently, SMT is driving the development of PCB substrate materials with improved thermal and electrical properties. In our continuing effort to meet these military demands, we evaluated high-temperature resistant/high-performance acetylene-terminated polyimide composites for use in SMT PCBs. This paper focusses on the processing and on the thermal, thermomechanical, and dynamic mechanical properties data developed for these acetylene-terminated polyimide composites for their potential evaluation as PCBs. The characterization includes such properties as in-plane coefficient of thermal expansion (CTE), out-of-plane CTE, and glass transition temperature (Tg), which determine the solder joint reliability, plated-through-hole (PTH) reliability, and dimensional stability.

scholarly journals Research on Performance Test System of Space Harmonic Reducer in High Vacuum and Low Temperature Environment

Machines ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 1
Author(s):  
Jing Wang ◽  
Zhihua Wan ◽  
Zhurong Dong ◽  
Zhengguo Li
Keyword(s):  
Low Temperature ◽  
High Speed ◽  
Performance Test ◽  
High Reliability ◽  
High Vacuum ◽  
Test System ◽  
Low Noise ◽  
Speed Ratio ◽  
Space Harmonic ◽  
Temperature Environment

The harmonic reducer, with its advantages of high precision, low noise, light weight, and high speed ratio, has been widely used in aerospace solar wing deployment mechanisms, antenna pointing mechanisms, robot joints, and other precision transmission fields. Accurately predicting the performance of the harmonic reducer under various application conditions is of great significance to the high reliability and long life of the harmonic reducer. In this paper, a set of automatic harmonic reducer performance test systems is designed. By using the CANOpen bus interface to control the servo motor as the drive motor, through accurately controlling the motor speed and rotation angle, collecting the angle, torque, and current in real time, the life cycle test of space harmonic reducer was carried out in high vacuum and low temperature environment on the ground. Then, the collected data were automatically analyzed and calculated. The test data of the transmission accuracy, backlash, and transmission efficiency of the space harmonic reducer were obtained. It is proven by experiments that the performance data of the harmonic reducer in space work can be more accurately obtained by using the test system mentioned in this paper, which is convenient for further research on related lubricating materials.

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