Coreless Substrate Design, Assembly and Reliability for High Speed Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001486-001513
Author(s):  
Jon Aday ◽  
Nozad Karim ◽  
Mike Devita ◽  
Steven Lee
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Core Layer ◽  
Power Delivery ◽  
Advanced Materials ◽  
Band Width ◽  
Electrical Performance ◽  
Next Generation ◽  
Reliability Data ◽  
The Core

There are 2 primary drivers for advanced substrate technologies to support the next generation of products. One driver is silicon designs which are shifting to 20–40 GBit applications. The band width of these products are requiring advanced materials, and designs which use much thinner cores making routing and manufacturing of these packages easier. The second driver is the move more advanced silicon nodes which also drives the importance for much better power delivery. Coreless substrates enable both of these applications by eliminating the core layer which enables much finner via pitchs to route signals and power/gnd planes. The thinness also reduces the bandwidth used up by the substrate which also enables better electrical performance. This paper will focus on the electrical drivers including simulation to support the structure, flip chip assembly of the package as well as the reliability data associated with the assembly.

Z-axis Interconnections for Next Generation Packaging

2011 ◽  
Vol 2011 (1) ◽  
pp. 000469-000475
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
John M. Lauffer ◽  
Tim Antesberger ◽  
Voya R. Markovich
Keyword(s):  
Flip Chip ◽  
Electrical Performance ◽  
Next Generation ◽  
Low Loss ◽  
Electrically Conducting ◽  
S Parameter ◽  
Plastic Ball ◽  
Materials Used ◽  
Electrically Conducting Adhesives

In this paper, the use of electrically conducting adhesives (ECA) to form z-axis interconnections for next generation packaging is discussed. In particular, current efforts related to Z-axis interconnections for device level fabrication, integration, and electrical performance are highlighted. A few optimized ECAs were used for hole fill applications to fabricate Z-axis interconnections in laminates. Conductive joints were formed during composite lamination using the ECA. Around 5,000 to 200,000 through holes in the joining cores, formed by laser or mechanical drilling, and having diameters ranging from 50 μm to 750 μm, were filled with an optimized conducting adhesive. The adhesive-filled joining cores/layers were laminated with circuitized subcomposites to produce a composite structure. As a case study, a variety of z-axis interconnect constructions for a flip-chip plastic ball grid array package, rigid-flex, rigid-rigid, package-interposer-package (PIP), RF structures, and PWBs were fabricated and evaluated at both the subcomposite and composite levels to understand structural and electrical integrity. Electrically, S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES up to 15 Gbps over 750 mm. The present process allows fabrication of z-interconnect conductive joints having diameters in the range of 55 to 500 μm. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

scholarly journals Numerical Assessment of a Sustainable Blast Protection Wall

2021 ◽  
Vol 14 (4) ◽  
pp. 37-49
Author(s):  
Ali Ghalib ◽  
Assal Hussein
Keyword(s):  
Human Life ◽  
Low Cost ◽  
Core Layer ◽  
Recycled Aggregate ◽  
Advanced Materials ◽  
Wall Structure ◽  
Blast Protection ◽  
The Core ◽  
Blast Response ◽  
Plane Displacement

Terrorist attacks have increased in the past few years in different countries. Explosions are problem that has significant impact on human life, as well as the social and economic situations. Engineers have designed targeted structures to mitigate blast effects. However, design blast-resistant systems is pricey and not suitable choice in most cases. Therefore, install blast barriers to protect occupants and instructed can reduce casualties and losses. Most current studies have investigated the performance of multi-layer composite blast barriers composed of advanced materials, which is not only costly, but require skilled labour to construct. The present study conducts numerical analysis of eco-friendly composite blast protection wall to mitigate blast. The wall structure consists of two face-sheet of adobe brick and core layer of crushed recycled aggregate. The analysis framework includes three different blast wall models using ABAQUS®. The explosive charge of 1-kilogram TNT is placed at different standoff distances from 0.25 to 4.0 meter in front of the wall. The authors conclude sustainable materials to design blast barriers could be effective in reducing the intensity of explosions in certain blast scenarios. The thickness of the core layer and standoff distance have the main contribution to identify the blast response of the blast wall. For instance, the calculated out-of-plane displacement results showed when 1- kg TNT place at 0.5-m from the wall, and thickness of the core increases from 30-cm to 60-cm, the displacement decreases by 38.74%. While the acceleration decreases by 75% for the same range of increase of thickness of the core layer. The present study calls researchers to investigate the performance of low-cost, and environment-friendly materials to attenuate abnormal loads wether are man-made or natural hazards.

Next-Generation Lead-Free Solder Plating Products for High Speed Bumping, Capping and Micro-Capping Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000458-000460
Author(s):  
Jonathan Prange ◽  
Julia Woertink ◽  
Yi Qin ◽  
Pedro Lopez Montesinos ◽  
Inho Lee ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Lower Cost ◽  
Lead Free ◽  
Height Distribution ◽  
Lead Free Solder ◽  
Next Generation ◽  
Organic Additives ◽  
Microelectronic Devices ◽  
Free Solder

Flip-chip interconnect and 3-D packaging applications must utilize reliable lead-free solder joints in order to produce highly efficient, advanced microelectronic devices. The solder alloy most commonly utilized for these applications is SnAg, which is typically deposited by electroplating due to lower cost and greater reliability as compared to other methods. The electroplating performance and robustness of SnAg products for bumping and capping applications is highly dependent on the organic additives used in the process. Here, next-generation SnAg products that improve the rate of solder electrodeposition without compromising key requirements such as tight Ag% control, uniform height distribution and smooth surface morphology will be discussed. These plated solders were then evaluated for compatibility with bumping, capping and micro-capping applications.

Large Flip Chip Assembly Challenges and Risk Mitigation Process

2017 ◽  
Author(s):  
Jeremy Plunkett ◽  
Suresh Subramaniam ◽  
Nokibul Islam ◽  
Kang KeonTaek ◽  
Gu SeonMo ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Risk Mitigation ◽  
Large Body ◽  
The Body ◽  
Network Communication ◽  
Next Generation ◽  
High Speed Network ◽  
Body Sizes ◽  
Package Reliability

Next generation high speed network/communication packages require much larger die sizes and increased ball counts (>3000) to meet high speed, high input/output (I/O) functionality and improved reliability performance. Demand for such high speed large flip chip packages create an opportunity for highly integrated multi-chip modules (MCM’s) and 2.5D/3D silicon (Si) interposer packages which are gradually emerging to meet these requirements. Achieving both increased margins in the power delivery network and increased functionality in next generation high speed network/communication applications requires extremely efficient, low loss package designs with body sizes 50×50mm or larger. One of the biggest challenges for such large die, large body packages is how effectively the assembly risk can be mitigated while fulfilling long term package reliability and functionality. The work presented in this paper describes key factors for mitigating several assembly related issues in the industry, including package warpage/co planarity, and the identification of the optimum processes and materials for successfully manufacturing large body flip chip packages with high assembly yields. As the body sizes and die sizes increase, the chip-to-package interaction failure risk increases significantly due to a larger distance to neutral point (DNP). Typical assembly risks are extreme low-k (ELK) delamination (white bumps) during the chip joining process, bump tearing or cracking, underfill delamination, and warpage issues. A comprehensive experiment was carried out to achieve the objective of the work. A test vehicle was developed using a 21×22mm2, flip chip copper (Cu) column bumped die placed onto a 50×50mm body size, using a multi-layer substrate with full array BGA footprint and ample passive components in the package. Processes were developed to optimize assembly yield and package reliability, including an extensive board level reliability test. Assembly materials were selected to achieve excellent assembly yield, high thermo-mechanical reliability, and increased package functionality.

Future Direction and Challenges for Microelectronics Packaging Materials

2005 ◽  
Author(s):  
Vijay Wakharkar ◽  
J. C. Matayabas
Keyword(s):  
High Speed ◽  
Power Delivery ◽  
Thermal Dissipation ◽  
Advanced Materials ◽  
Packaging Materials ◽  
High Demand ◽  
Microelectronics Packaging ◽  
Advanced Packaging ◽  
New Methodologies ◽  
Future Direction

The continual increasing performance of microelectronics products places a high demand on packaging technologies. This presentation will discuss the current environment, challenges, and technologies being pursued. Package technology migrations for microprocessors and communication products are described. Material needs for high thermal dissipation, high-speed signaling, and high-density interconnects are discussed. Microprocessor scaling for increased performance and reduced cost places significant challenges on power delivery and power removal due to reducing dimensions, operating voltages, and increasing power. Meeting these challenges indicates a need for advanced packaging solutions using advanced materials. New methodologies, metrologies, and materials/process technologies to address these challenges are also highlighted.

Material and Process Developments for Robust and High Reliability Glass Wafers for 2.5D Packaging

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001364-001377
Author(s):  
Roupen Keusseyan ◽  
Tim Mobley
Keyword(s):  
Borosilicate Glass ◽  
High Speed ◽  
High Reliability ◽  
Electrical Performance ◽  
Next Generation ◽  
Wafer Level ◽  
Hole Formation ◽  
Heterogeneous Devices ◽  
Primary Key ◽  
Through Hole

Borosilicate glass based wafer technologies are being developed for next generation high speed electronic, telecom and biotech systems; that integrate heterogeneous devices in a single package for improved electrical performance. The primary key to success is to have a well understood via through the glass that can be used as a core to build wafer level packages from. The present paper will discuss developments in through hole formation technology and via metallization materials and processes. Through hole formation in borosilicate glass with corresponding wall morphology and chemistry play important roles in building robust vias through the glass. These hole characteristics and their dependence on performance, defects at the wafer level and key developments that have been achieved to overcome them will be discussed in detail.

SOLDERABLE ANISOTROPIC CONDUCTIVE ADHESIVES FOR 3D PACKAGE APPLICATIONS

2014 ◽  
Vol 2014 (1) ◽  
pp. 000165-000169
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Low Cost ◽  
Organic Substrate ◽  
Advanced Materials ◽  
Assembly Process ◽  
Conductive Adhesives ◽  
Bump Height ◽  
3D Packaging ◽  
3D Package

3D packaging has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize devices and meet the demand of high speed, provide more memory, more function and low cost. With the advancement of 3D packaging, the bump height is now down from 80μ to 10μ. When the bump diameter is 20–40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however underfill won't help assembly process. In order to resolve some difficulties that 3D packaging faces, YINCAE Advanced Materials, LLC has developed solderable anisotropic conductive adhesives for 3D package applications. In this paper we will discuss the assembly process and reliability in detail.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

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