Acetylene-Terminated Polyimide Composites for Advanced Electronic Packaging Applications

1989 ◽  
Vol 154 ◽  
Author(s):  
A. Mahammad Ibrahim
Keyword(s):  
Electronic Packaging ◽  
High Speed ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
High Reliability ◽  
Circuit Board ◽  
Electrical Performance ◽  
Surface Mount ◽  
Plated Through Hole ◽  
Polyimide Composites

AbstractSurface mount technology (SMT) is an electronic packaging technology wherein the leads of electronic components are soldered directly to metallized pads on the surface of a printed circuit board (PCB). The SMT with leadless ceramic chip carriers (LCCCs) is used to design, fabricate, and assemble affordable, high-speed, high-density electronic modules with reduced size and weight and improved electrical performance. In surface mount devices, the LCCCs are soldered directly onto the fabric composite PCB substrate. New high-performance composite substrate materials must be developed to take full advantage of SMT. Fabricating a PCB that will perform reliably throughout its intended life is also an increasingly important requirement, especially if the goal is to satisfy the high reliability required in military applications. Consequently, SMT is driving the development of PCB substrate materials with improved thermal and electrical properties. In our continuing effort to meet these military demands, we evaluated high-temperature resistant/high-performance acetylene-terminated polyimide composites for use in SMT PCBs. This paper focusses on the processing and on the thermal, thermomechanical, and dynamic mechanical properties data developed for these acetylene-terminated polyimide composites for their potential evaluation as PCBs. The characterization includes such properties as in-plane coefficient of thermal expansion (CTE), out-of-plane CTE, and glass transition temperature (Tg), which determine the solder joint reliability, plated-through-hole (PTH) reliability, and dimensional stability.

Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000141-000147 ◽  
Author(s):  
John M. Lauffer ◽  
Kevin Knadle
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Performance Enhancement ◽  
High Density ◽  
Consumer Electronics ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Electrically Conductive Adhesive ◽  
Plated Through Hole ◽  
Interconnect Technology

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

Multiple CMOS Intersection Measuring System Modeling and Analysis

2012 ◽  
Vol 614-615 ◽  
pp. 1299-1302
Author(s):  
Ming Jing Li ◽  
Yu Bing Dong ◽  
Guang Liang Cheng
Keyword(s):  
High Speed ◽  
High Performance ◽  
High Reliability ◽  
System Modeling ◽  
Position Effect ◽  
Field Of View ◽  
Measuring System ◽  
Price Ratio ◽  
Matlab Simulation ◽  
Modeling And Analysis

Multiple high speed CMOS cameras composing intersection system to splice large effect field of view(EFV). The key problem of system is how to locate multiple CMOS cameras in suitable position. Effect field of view was determined according to size, quantity and dispersion area of objects, so to determine camera position located on below, both sides and ahead to moving targets. This paper analyzes effect splicing field of view, operating range etc through establishing mathematical model and MATLAB simulation. Location method of system has advantage of flexibility splicing, convenient adjustment, high reliability and high performance-price ratio.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

Effective Friction Control for Optimization of High Speed Rail Operations

2010 ◽  
Author(s):  
Donald T. Eadie ◽  
Kevin Oldknow ◽  
Yasushi Oka ◽  
Ron Hui ◽  
Peter Klauser ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
High Reliability ◽  
Ride Quality ◽  
Oil And Grease ◽  
High Speed Rail ◽  
Wear Rates ◽  
Friction Control ◽  
Very High ◽  
Effective Friction

Expected growth of High Speed Rail (HSR) in North America will in many instances involve operation on existing infrastructure, shared with other traffic. This will pose many challenges, not least of which will be wheel and rail wear, and ride quality. This paper addresses how effective friction control can be employed to mitigate these factors and provide an important tool to the designers of new systems. Case studies describe successful use of train mounted solid stick LCF flange lubrication on high speed trains in East Asia and Japan. In each case, higher speed train operation has involved operation on areas of track with greater curvature than usual on dedicated high speed track. Appropriately designed LCF systems provide an inherently very high level of reliability and very low flange wear rates. Use of dry thin film lubricant technology has advantages over use of liquid lubricants (oil and grease) which can experience splash and fling off at high train speeds. Train mounted solid sticks provide greater consistency / reliability and ease of maintenance compared with wayside gauge face lubrication. Complementing practical field experience, modeling studies are presented which show the potential of high performance flange lubrication to allow for additional flexibility in designing wheel profiles for high speed rail. The ideal profile will balance vehicle stability (benefiting from lower conicity) and curving performance (benefiting from higher conicity). In a high speed train with long wheel base and high suspension stiffness operating in areas with significant curvature, finding an appropriate compromise becomes even more challenging than usual. Controlling flange wear at low rates with highly effective solid stick lubrication offers the opportunity to use wheel profiles providing lower effective conicity and therefore better ride quality, without compromising wheel life. This approach will be practical only in a scenario where a very high reliability wheel / rail lubrication system is employed.

Anti-Counterfeit, Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

2013 ◽  
Vol 2013 (1) ◽  
pp. 000158-000165
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
How Lin
Keyword(s):  
High Speed ◽  
High Reliability ◽  
Electronic Devices ◽  
Implantable Devices ◽  
High Density ◽  
Electrical Performance ◽  
Recent Developments ◽  
Speed Performance ◽  
Advanced Packaging ◽  
Silicone Coatings

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. This paper discusses the development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for miniaturized electronic devices. In particular, recent developments in high density interconnect (HDI) substrate technology are highlighted. System-in-Package (SiP), embedded passives, stacked packages, and flex substrates are utilized to achieve significant reduction in size, weight, and power (SWaP) consumption in electronic devices. The paper also describes a novel approach for the fabrication of silicone-coated flexible substrates to provide biocompatibility for implantable devices. In particular, we highlight recent developments on silicone coatings on high density, miniaturized polyimide-based flexible electronics. A variety of high density circuits ranging from 11 microns lines/space to 25 microns lines/spaces were processed on polyimide flex substrates and subsequently coated with biocompatible silicone coatings. The electrical performance of silicone coated batteries was characterized by voltage measurements. The final structure enhances the stretching capability. Fabrication of advanced medical substrates incorporating technologies for parts authentication (anticounterfeit measures) such as embedded signature circuits and use of nano or micro materials as signatures are discussed. In some instances, these measures do not add cost to package fabrication.

High Temperature Silicon Carbide Power Modules for High Performance Systems

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000159-000166 ◽  
Author(s):  
J. Hornberger ◽  
B. McPherson ◽  
J. Bourne ◽  
R. Shaw ◽  
E. Cilio ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
High Speed ◽  
High Performance ◽  
High Reliability ◽  
Extreme Environment ◽  
High Energy ◽  
Energy Applications ◽  
Power Modules ◽  
Reliability Systems

The demands of modern high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of silicon carbide (SiC) are well known, including high temperature operation, high voltage blocking capability, high speed switching, and high energy efficiency. In this discussion, APEI, Inc. presents two newly developed high performance SiC power modules for extreme environment systems and applications. These power modules are rated to 1200V, are operational at currents greater than 100A, can perform at temperatures in excess of 250 °C, and are designed to house various SiC devices, including MOSFETs, JFETs, or BJTs. One newly developed module is designed for high performance, ultra-high reliability systems such as aircraft and spacecraft, and features a hermetically sealed package with a ring seal technology capable of sustaining temperatures in excess of 400°C. The second module is designed for high performance commercial and industrial systems such as hybrid electric vehicles or renewable energy applications, implements a novel ultra-low parasitic packaging approach that enables high switching frequencies in excess of 100 kHz, and weighs in at just over 130 grams (offering ~5× mass reduction and ~3× size reduction in comparison with industry standard power brick packaging technology). It is configurable as either a half or full bridge converter. In this discussion, APEI, Inc. introduces these products and presents practical testing of each.

Materials Characterization and Model of PCB Thermal Expansion for Laminates With Various Copper Densities and Thicknesses

2004 ◽  
Author(s):  
William J. Cunningham ◽  
Dick Casali ◽  
Norman J. Armendariz
Keyword(s):  
Thermal Expansion ◽  
Thermal Management ◽  
High Speed ◽  
Printed Circuit Board ◽  
Coefficient Of Thermal Expansion ◽  
Materials Characterization ◽  
Circuit Board ◽  
Printed Circuit ◽  
Printed Circuit Board Manufacturing ◽  
Increasing Temperature

Abstract The SEMATECH/SEMI roadmap forecasts increased density requirements for printed circuit board manufacturing to accommodate smaller form factor interconnects, increased pin counts, and routing densities on a range of PCB sizes and thicknesses. As a result, the effect of materials. thermal expansion properties may further impact the structural or physical integrity and subsequent electrical properties for high speed and thermal management requirements. This study demonstrated that various sample coupons selected from PCB boards with different amounts of copper showed a corresponding coefficient of thermal expansion (CTE) correlation in the Z-axis (CTEZ) and can be modeled using a constitutive equation. Moreover, samples were further evaluated from the effect of increasing temperature and showed that the CTE indeed affects copper-interconnect physical structures such as copper vias and barrels in terms of elongation or strain.

Critical Aspects of High-Performance Microprocessor Packaging

MRS Bulletin ◽  
2003 ◽  
Vol 28 (1) ◽  
pp. 21-34 ◽  
Author(s):  
Vasudeva P. Atluri ◽  
Ravi V. Mahajan ◽  
Priyavadan R. Patel ◽  
Debendra Mallik ◽  
John Tang ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Heat Dissipation ◽  
Printed Circuit Board ◽  
Power Input ◽  
Power Delivery ◽  
Circuit Board ◽  
Perspective View ◽  
Broad Perspective ◽  
Future Evolution

AbstractHistorically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.

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