The Package Becomes the System

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-36
Author(s):  
Bruce J. Barbara
Keyword(s):  
High Reliability ◽  
Electrical Performance ◽  
Entire System ◽  
Single System ◽  
Wafer Level ◽  
Electromechanical Systems ◽  
Thermal Structures ◽  
On Chip ◽  
3D Stacking ◽  
System Miniaturization

The benefits of system miniaturization lower-cost, higher electrical performance and better thermal mechanical reliability, than the current approach of discrete component packaging have been discussed at length. Several technologies have been used to address these benefits. SOC, SiP, Fan-In and Fan Out and wafer level packages. Recently there has been much discussion about Fan Out Wafer Level packaging (FOWLP) to integrate the entire system in package. However, actual implementations fall short of a complete system in a package in that only few of the chips and some passives are currently integrated into the FOWLP. But what about the rest of the system? A true system also requires additional components not traditionally considered integrate-able into a package. These include antennas, batteries, thermal structures, RF, Optical, micro-electromechanical systems (MEMs), and micro sensor functions. The current FOWLP package technology as discussed by the media falls short of this type of system integration due to limitations in the number of chips that can be integrated and the lack of sufficient interconnect layers to support these functions in a system. 3D stacking has also been employed to improve the SiP by adding memory components. These implementations are limited to stacking of identical chips with through hole silicon vias (TSV) located remotely from any circuitry. Aurora Semiconductor will introduce a packaging technology where the package becomes the system. We call this technology 4DHSiP™ or 4D Heterogeneous System in package. 4DHSiP™ is a system miniaturization technology in contrast to system on chip (SOC) at the integrated circuit level and system in package stacked ICs and packages (SIP) at the module level. 4DHSiP™ is considered an inclusive system technology in which, SIP, thermal structures and batteries are considered as substantive technologies. 3D stacking is no longer limited by the location of the TSV within the stacked components. Heterogeneous multi-chip sub module layers can be stacked to accommodate additional system components. These layers, when interconnected, form the entire system. By stacking sub module layers, specific component types can be located on the top most layer as needed by specific function (e.g. Bio functions, Optical functions, Antennas). An example of this type of module stacking used to create an optical based system will be shown.4DHSiP™ is a new, emerging system concept where the device, package, and system board are miniaturized into a single system package including all the needed system functions. Such a single system package with multiple heterogeneous ICs provides all the system functions by co-design and fabrication of digital, radiofrequency (RF), optical, micro-electromechanical systems (MEMS) in either the IC or the system package. 4DHSiP™ combines the best on chip and off chip integration technologies to develop ultra-miniaturized, high-performance, multifunctional products. A significant benefit of this miniaturization is the elimination of multiple sockets and connectors currently used to connect sub-systems together. This ultra-miniaturization of multiple to mega functions, ultrahigh performance, low cost and high reliability will be the way systems are designed in the future to achieve More than Moore.

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000916-000936
Author(s):  
Jemmy Sutanto ◽  
D. H. Kang ◽  
J. H. Yoon ◽  
K. S. Oh ◽  
Michael Oh ◽  
...  
Keyword(s):  
Form Factor ◽  
System Integration ◽  
Wire Bonding ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Face To Face ◽  
Parasitic Resistance ◽  
On Chip ◽  
Packaging Cost

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

High Reliability Fine Pitch WLCSP for High Pin Count Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001894-001907
Author(s):  
David Lawhead ◽  
Ronnie Yazzie ◽  
Tony Curtis ◽  
Guy Burgess ◽  
Ted Tessier
Keyword(s):  
Silver Content ◽  
High Reliability ◽  
Electrical Performance ◽  
Thermal Testing ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Industry Standard ◽  
Fine Pitch ◽  
Board Level ◽  
Board Level Reliability

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements. This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.

Material and Process Developments for Robust and High Reliability Glass Wafers for 2.5D Packaging

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001364-001377
Author(s):  
Roupen Keusseyan ◽  
Tim Mobley
Keyword(s):  
Borosilicate Glass ◽  
High Speed ◽  
High Reliability ◽  
Electrical Performance ◽  
Next Generation ◽  
Wafer Level ◽  
Hole Formation ◽  
Heterogeneous Devices ◽  
Primary Key ◽  
Through Hole

Borosilicate glass based wafer technologies are being developed for next generation high speed electronic, telecom and biotech systems; that integrate heterogeneous devices in a single package for improved electrical performance. The primary key to success is to have a well understood via through the glass that can be used as a core to build wafer level packages from. The present paper will discuss developments in through hole formation technology and via metallization materials and processes. Through hole formation in borosilicate glass with corresponding wall morphology and chemistry play important roles in building robust vias through the glass. These hole characteristics and their dependence on performance, defects at the wafer level and key developments that have been achieved to overcome them will be discussed in detail.

scholarly journals Design and Implementation of SOC-Based Noncontact-Type Level Sensing for Conductive and Nonconductive Liquids

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
J. L. Mazher Iqbal ◽  
Munagapati Siva Kishore ◽  
Arulkumaran Ganeshan ◽  
G. Narayan
Keyword(s):  
Printed Circuit Board ◽  
System On Chip ◽  
Circuit Board ◽  
Sensor Technology ◽  
Electromechanical Systems ◽  
Printed Circuit ◽  
Design And Implementation ◽  
Hardware System ◽  
On Chip

In contrast to the existing electromechanical systems, the noncontact-type capacitive measurement allows for a chemically and mechanically isolated, continuous, and inherently wear-free measurement. Integration of the sensor directly into the container’s wall offers considerable savings potential because of miniaturization and installation efforts. This paper presents the implementation of noncontact (NC)-type level sensing techniques utilizing the Programmable System on Chip (PSoC). The hardware system developed based on the PSoC microcontroller is interfaced with capacitive-based printed circuit board (PCB) strip. The designer has the choice of placing the sensors directly on the container or close to it. This sensor technology can measure both the conductive and nonconductive liquids with equal accuracy.

Wafer-Level Contactless Testing Based on UHF RFID Tags With Post-Process On-Chip Antennas

2018 ◽  
Vol 65 (10) ◽  
pp. 1355-1359 ◽  
Author(s):  
Alessandro Finocchiaro ◽  
Giovanni Girlando ◽  
Alessandro Motta ◽  
Alberto Pagani ◽  
Egidio Ragonese ◽  
...  
Keyword(s):  
Rfid Tags ◽  
Uhf Rfid ◽  
Wafer Level ◽  
Post Process ◽  
Contactless Testing ◽  
On Chip

Ecosystems in Zones of Conflict: The Case for Bandwidth Management

2002 ◽  
Author(s):  
Michel J. G. van Eeten ◽  
Emery Roe
Keyword(s):  
Ecosystem Management ◽  
High Reliability ◽  
Professional Group ◽  
Professional Culture ◽  
Detailed Knowledge ◽  
Entire System ◽  
High Reliability Organizations ◽  
Bandwidth Management ◽  
External Disturbances ◽  
Professional Representation

What profession that is core to ecosystem management is described in the following passage? . . . [Their professional] representation of a . . . system can be typified as physical, holistic, empirical, and fuzzy; . . . [treating] the system more as a whole than in terms of individual pieces; ... [expecting] uncertainty rather than deterministic outcomes...; [taking] uncertainty or “fuzziness” . . . to be inevitable and, to some degree, omnipresent; [seeing] ambiguity . . . pervade the entire system, and . . . [suspecting] the unsuspected at every turn. . . . [T]he underlying notion [in their professional culture] is that no amount of rules and data can completely and reliably capture the actual complexity of the system . . . [I]t is more important . . . for [these professionals] to maintain an overview of the behavior of the whole system than to have detailed knowledge about its components. . . . [They] tend to be very wary of [the pressure to intervene], primarily because it runs counter to a basic attitude of conservatism fostered by their culture: “when in doubt, don’t touch anything.” Their reluctance to take any action unless it is clearly necessary arises from the awareness that any operation represents a potential error, with potentially severe consequences. (Von Meier 1999, pp. 104-107) . . . We suspect that many readers would see ecologists (writ large again) as the professional group whose views are being described. Ecologists, as we have seen, frequently describe the ecosystem in just such terms: it responds to external disturbances, the whole system is more than the sum of its parts, it displays nondeterministic behavior, its complexity can never be fully captured and, therefore, management is extremely challenging, with managers always reluctant to intervene—at least in major ways—in ecosystems they do not know, because this potentially creates more problems than it solves. However, ecologists are not the group being described, and here is the surprise. Though the quoted phrases are almost textbook ecology material, the professional culture discussed here is in fact that of line operators in high reliability organizations (HROs).

Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices”

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000383-000407
Author(s):  
Kevin Moody ◽  
Nick Stukan
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
High Reliability ◽  
Semiconductor Industry ◽  
Thermal Dissipation ◽  
System Level ◽  
Electrical Performance ◽  
Power Devices ◽  
Embedded Technology ◽  
New Device

In this paper will focus on the comprehension of System-in-Package (SiP) with embedded active and passive components integration will be described. Embedding of semiconductor chips into substrates provides many advantages that have been noted. It allows the smallest package form-factor with high degree of miniaturization through sequentially stacking of multiple layers containing embedded devices that are optimized for electrical performance with short and geometrically well controlled copper interconnects. In addition, the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability at system level. Furthermore, embedded technology is an excellent resolution to Power management challenges dealing with new device technologies (Si, GaS, GaN) and optimization on the thermal dissipation with improved efficiency. Embedded technology comes with many challenges in 2019, primarily design for manufacturability (DFM) and maturity. Customers are looking for better-performance capability and pricing normally that means same or lower than die free package cost (DFPC) comparison. This paper will discuss the challenges bring to market the Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices” Today, the embedded process is being developed by printed circuit board (PCB) manufacturers creating a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models. As a result of the increasing interest in implementing embedding technologies, ACCESS Semiconductors in China is committed to be a leader in the adaptation of embedding technologies, with over 10-yrs mature coreless technology and proved design rules for low profile dimensions with seamless Ti/Cu sputtering and Cu pillar interconnect giving advantages in both electrical & power performance. ACCESS Patented “Via-in-Frame” technology provides High Reliability (MSL1, PCT, BHAST) at Cost Effective in high panel utilization for HVM, using standard substrate/PCB known material sets, no need for wafer bumping/RDL, over-mold or under-fill cost adders. ACCESS Semiconductors is currently in HVM on single die 2L, and LVM on multi-devices actives/passives 4L SiP construction both platforms are driven from the power market segment. In-development on Die Last & Frameless (MeSiP) platforms utilizing hybrid technology (mSAP) and Photo Imageable Dielectric (PID) materials for cost down solutions in HVM by Q1FY2020. Also, ACCESS Semiconductors total turn-key solutions will include front-of-line (FOL) and end-of-line (EOL) capability from wafer handling, back-grinding, and dicing with KGD traceability thru the embedded chip process, frame/strip singulation, FT, marking pack & ship providing additional 30% cost reduction in the future. Here's an illustration of Embedded Technology Roadmap and Product Platforms.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

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