Evaluation of die to organic laminate to PCB interconnects up to 50GHz

2019 ◽  
Vol 2019 (1) ◽  
pp. 000223-000227
Author(s):  
Selaka Bulumulla ◽  
Koushik Ramachandran
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Substrate Material ◽  
Circuit Board ◽  
Test Vehicle ◽  
Ceramic Substrates ◽  
High Frequencies ◽  
Multiple Levels ◽  
High Frequency Performance ◽  
High Density Packaging

Abstract Ceramic substrates have traditionally been used in RF and microwave packaging applications because of the electrical properties at high frequencies. However, there is significant interest in using organic laminates due to its tighter wiring ground rules for high density packaging and lower cost of fabrication. The high frequency performance of interconnection from die to PCB using an organic packaging substrate has not yet been studied in detail. In this work, the interconnect performance of die to organic laminate to PCB up to 50 GHz was modeled and characterized using a test vehicle assembly. The test vehicle was specifically designed with test pads to characterize the interconnect performance at multiple levels of interconnection. A comparison study using a ceramic package substrate was also carried out. The modeling and hardware testing results from this study showed −3dB bandwidth of more than 50GHz for printed circuit board (PCB) to organic laminate and a bandwidth of 40GHz for the die to organic laminate to PCB interconnection. The results from this study showed that the organic laminate demonstrated a high frequency performance comparable to that of the ceramic substrate, which makes it suitable as a packaging substrate material for high frequency applications.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

scholarly journals Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1495
Author(s):  
Loris Pace ◽  
Nadir Idir ◽  
Thierry Duquesne ◽  
Jean-Claude De Jaeger
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Power Converters ◽  
Calibration Procedure ◽  
Circuit Board ◽  
Design System ◽  
Switching Speed ◽  
Parasitic Inductance ◽  
Frequency Converters ◽  
S Parameters

Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board

2018 ◽  
Vol 2018 (1) ◽  
pp. 000384-000388
Author(s):  
Brian Curran ◽  
Jacob Reyes ◽  
Christian Tschoban ◽  
Ivan Ndip ◽  
Klaus-Dieter Lang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Antenna Arrays ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Front End ◽  
High Bandwidth ◽  
Increasing Demand ◽  
K Band

Abstract Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.

Electrical Characterization of Low-Profile Copper Foil for Reduced Surface Roughness Loss

2016 ◽  
Vol 2016 (1) ◽  
pp. 000358-000363 ◽  
Author(s):  
Qianfei Su ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Surface Roughness ◽  
Cross Sections ◽  
Transmission Lines ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Electrical Characterization ◽  
Cavity Resonator ◽  
Circuit Board ◽  
Low Profile ◽  
Measure Surface Roughness

Abstract Signal attenuation in transmission lines is a major issue for reliable transmission in high frequency range. Knowledge of the electrical parameters of printed circuit board (PCB), including dielectric constant and loss tangent, is critical. Moreover, surface roughness has a great effect on loss in high frequency. This paper demonstrates an effective simulation fitting method for electrical material characterization. Cavity resonator is chosen as the circuit for characterization. A methodology is presented to measure surface roughness from cross sections, and compared with values extracted from resonator measurements. Several materials and copper foils treatments, including low-profile, are analyzed in this paper.

Flip Chip Thermal Test Vehicle Design: Requirements, Evaluations, and Validations

2003 ◽  
Author(s):  
Teck Joo Goh ◽  
Chia-Pin Chiu ◽  
K. N. Seetharamu ◽  
G. A. Quadir ◽  
Z. A. Zainal
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Thermal Characterization ◽  
Circuit Board ◽  
Vehicle Design ◽  
Test Chip ◽  
Test Vehicle ◽  
Design Processes ◽  
Thermal Test ◽  
Design Requirements

This paper reviews the design of a flip chip thermal test vehicle. Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn-in simulation are outlined. The design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. In addition, the design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also illustrated. The design considerations and processes of the package substrate and printed circuit board with special emphasis on the physical routing of the thermal test chip structures are described. These design processes are supported with thermal data from various finite-element analyses (FEA) carried out to evaluate the capability and limitations of thermal test vehicle design. Design optimization as the outcome of these analyses is also elaborated. Lastly, the validation and calibration procedures of the thermal test vehicle are presented in this paper.

A Design of Printed Inverted-F Antenna for RFID Tag at 5.8 GHz

2013 ◽  
Vol 427-429 ◽  
pp. 1293-1296
Author(s):  
Yan Zhong Yu ◽  
Ji Zhen Ni ◽  
Xian Hui Li
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Ground Plane ◽  
Simulation Software ◽  
Circuit Board ◽  
Electromagnetic Simulation ◽  
Antenna Structure ◽  
Rfid Tag ◽  
Printed Circuit ◽  
Substrate Layer

A printed inverted-F antenna for RFID tag at 5.8 GHz is designed in this paper. The antenna structure consists of an inverted-F patch, a substrate layer, and a ground plane. To reduce costs, the FR4 is selected as the material of substrate layer, which is used commonly in PCB (Printed Circuit Board). Its relative permittivity is 4.4 and a loss tangent is 0.02. The inverted-F patch and ground plane are laid on/under the substrate layer respectively. The designed antenna is modeled, simulated and optimized by using HFSS (high frequency electromagnetic simulation software). Simulation results demonstrate that the printed inverted-F antenna can satisfy the requirements of RFID Tag applications.

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