Gate Driver Design in a 1 μm SiC CMOS Process for Heterogeneous Integration Inside SiC Power Module

In this paper, the design and implementation of a gate driver in SiC CMOS process is presented for heterogeneous integration (HI) inside the commercial SiC power module. The output stage of the gate driver circuit includes four-pull up (QP 1,2,3,4) and four-pull down (QN 1,2,3,4) transistors to vary current drive strength. The output stages are driven by tri-state buffer chains that are controlled by comparator based control circuits. The driver is tested over temperature up to 300°C. At higher temperatures, the peak drive current (under full strength with no external load) increases with the output swing remaining the same. Variation of the driver’s output pull-up and pull-down stage at higher load capacitance is also discussed in this paper. The driver circuit layout is optimized to utilize the maximum die area allowed by the process. The gate driver layout is 4.8mm × 4.8mm. The bond pads and layout orientation are configured for flip-chip packaging but can also be used for wire-bonding.