High-Temperature Trench Capacitors, Using Thin-Film ALD Dielectrics

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000130-000133 ◽  
Author(s):  
Dorothee Dietz ◽  
Yusuf Celik ◽  
Andreas Goehlich ◽  
Holger Vogt ◽  
Holger Kappert
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Automobile Industry ◽  
Elevated Temperatures ◽  
Atomic Layer ◽  
Operating Voltage ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Layer Deposition ◽  
Soft Breakdown

High-temperature passive electronic becomes more and more important, e.g. in the field of deep drilling, aerospace or in automobile industry. For these applications, capacitors are needed, which are able to withstand temperatures up to 300 °C, which exhibit a low leakage current at elevated temperatures, a breakdown voltage above the intended operating voltage and a high capacitive density value. In this paper, investigations of 3D-integration and atomic layer deposition (ALD) techniques to achieve these features are presented. A highly n-doped Si-substrate acts as a bottom electrode. Medium- and high-k dielectrics represent the insulator and the upper electrode consists of Ru, TiN or TiAlCN. The materials can be used at elevated temperatures. At room temperature, the leakage current is less than 10 pA/mm2 without showing a soft-breakdown up to ± 15 V, indicating the absence of Fowler-Nordheim tunneling. At 300 °C and at 3 V the leakage current amounts about 1 nA/mm2 and at 5 V a soft-breakdown is detected.

Atomic layer deposition of gadolinium scandate films with high dielectric constant and low leakage current

2006 ◽  
Vol 89 (13) ◽  
pp. 133512 ◽  
Author(s):  
Kyoung H. Kim ◽  
Damon B. Farmer ◽  
Jean-Sebastien M. Lehn ◽  
P. Venkateswara Rao ◽  
Roy G. Gordon
Keyword(s):  
Dielectric Constant ◽  
Atomic Layer Deposition ◽  
Leakage Current ◽  
High Dielectric Constant ◽  
Atomic Layer ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Layer Deposition ◽  
High Dielectric

MIM Capacitors Using ALD Al2O3 for RF IC and DRAM Applications

2004 ◽  
Vol 833 ◽  
Author(s):  
Sung Yong Ko ◽  
Jung Ik Oh ◽  
Joung Cheul Choi ◽  
Kang Hee Lee ◽  
Young Ho Bae ◽  
...  
Keyword(s):  
Leakage Current ◽  
Coplanar Waveguide ◽  
Atomic Layer ◽  
Good Reliability ◽  
Voltage Coefficient ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Layer Deposition ◽  
Metal Insulator Metal ◽  
Mim Capacitors

ABSTRACTMetal-insulator-metal (MIM) capacitors were fabricated in a coplanar waveguide type using the Al2O3 thin film. The Al2O3 film was grown by atomic layer deposition(ALD) using Methyl-Pyrolidine-Tri-Methyl-Aluminum (MPTMA) and H2O on Ti. The capacitance per unit area of the fabricated MIM capacitor was 0.229 μF/cm2. And it had lower voltage coefficient of capacitance (VCC) and lower leakage current than that of Al2O3 MIM capacitor prepared by Al oxidation and Si3N4 MIM capacitor prepared by PECVD respectively. The fabricated Al2O3 MIM capacitors prepared by ALD exhibited low VCC, low leakage current, small frequency-dependent capacitance reduction, low temperature coefficient of capacitance (TCC) and good reliability. The characteristics of the device were suitable for RF ICs and DRAM.

Atomic layer deposition of high-permittivity TiO2dielectrics with low leakage current on RuO2in TiCl4-based processes

2012 ◽  
Vol 27 (7) ◽  
pp. 074007 ◽  
Author(s):  
Jaan Aarik ◽  
Boris Hudec ◽  
Kristina Hušeková ◽  
Raul Rammula ◽  
Aarne Kasikov ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Leakage Current ◽  
Atomic Layer ◽  
High Permittivity ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Layer Deposition

scholarly journals Characterization of Electrical Traps Formed in Al2O3 under Various ALD Conditions

Materials ◽  
2020 ◽  
Vol 13 (24) ◽  
pp. 5809
Author(s):  
Md. Mamunur Rahman ◽  
Ki-Yong Shin ◽  
Tae-Woo Kim
Keyword(s):  
Leakage Current ◽  
Deposition Temperature ◽  
Fundamental Property ◽  
Frequency Dispersion ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Semiconductor Interface ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Deposited Film

Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.

Ultra-Thin Sputtered Pzt Films for Ulsi Drams

1993 ◽  
Vol 310 ◽  
Author(s):  
Jiyoung Kim ◽  
C. Sudhama ◽  
Rajesh Khamankar ◽  
Jack Lee
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Leakage Current Density ◽  
Current Density ◽  
Perovskite Phase ◽  
Storage Capacitor ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Pzt Thin Film ◽  
Pzt Films

AbstractIn this work, a high-temperature deposition technique has been developed for ultra-thin sputtered PZT films for ULSI DRAM (<256Mb) storage capacitor applications. In contrast to the previously developed low-temperature (200°C) deposition, deposition at high-temperature (400°C) yields a desirable reduction in grain size of the perovskite phase. The thickness of PZT films has been reduced to less than 30nm with high charge storage density (∼30μC/cm2) and low leakage current density. An optimized 65nm PZT thin film was found to have an equivalent SiO2 thickness of 1.9Å and a leakage current density of less than 10−6 A/cm2 under 2V operation.

Improvement of SBD Electronic Characteristics Using Sacrificial Oxidation Removing the Degraded Layer from SiC Surface after High Temperature Annealing

2007 ◽  
Vol 556-557 ◽  
pp. 877-880 ◽  
Author(s):  
Akimasa Kinoshita ◽  
Takashi Nishi ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Surface Condition ◽  
High Temperature Annealing ◽  
Reverse Voltage ◽  
Edge Termination ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Blocking Voltage ◽  
The Relationship

Ion implantation and a subsequent annealing at high temperature are required for fabricating a high voltage Schottky Barrier Diode (SBD) with a field limiting ring (FLR) or a junction termination extension (JTE), but high temperature annealing degrades surface condition of a SiC substrate and induces a degradation of electronic characteristics of a fabricated SBD. To avoid a degradation of SBD electronic characteristics after high temperature annealing, the method of removing a degraded layer from a SiC surface by sacrificial oxidation after high temperature annealing is studied. In this study, we studied the relationship between the improvement of SBD electronic characteristics and the thickness of sacrificial oxide grown after high temperature annealing. 9~12 SBD without edge termination were fabricated on a SiC substrate of 4mm×4mm. The ratio of good chips to all chips (9~12 SBD) increases with increasing total thickness of sacrificial oxide grown after high temperature annealing at 1800oC for 30 s, where an SBD with a leakage current less than 1μA/cm2 at reverse voltage of –100V was defined as a good chip. We applied this process growing sacrificial oxide of 150nm after high temperature annealing to fabricate the SBD with an FLR structure designed with 600V blocking voltage on a Si-face SiC substrate. The SBD with an FLR structure through this process of 150 nm sacrificial oxide is low leakage current of less than 1μA/cm2 at reverse voltage of –100V and achieves 600V blocking voltage, however, the SBD with an FLR structure without the process of sacrificial oxide after high temperature annealing is high leakage current at reverse voltage of –100V. It is shown that this process growing sacrificial oxide after high temperature annealing is useful to fabricate an SBD with an FLR structure.

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