Improvement of SBD Electronic Characteristics Using Sacrificial Oxidation Removing the Degraded Layer from SiC Surface after High Temperature Annealing

2007 ◽  
Vol 556-557 ◽  
pp. 877-880 ◽  
Author(s):  
Akimasa Kinoshita ◽  
Takashi Nishi ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda

Ion implantation and a subsequent annealing at high temperature are required for fabricating a high voltage Schottky Barrier Diode (SBD) with a field limiting ring (FLR) or a junction termination extension (JTE), but high temperature annealing degrades surface condition of a SiC substrate and induces a degradation of electronic characteristics of a fabricated SBD. To avoid a degradation of SBD electronic characteristics after high temperature annealing, the method of removing a degraded layer from a SiC surface by sacrificial oxidation after high temperature annealing is studied. In this study, we studied the relationship between the improvement of SBD electronic characteristics and the thickness of sacrificial oxide grown after high temperature annealing. 9~12 SBD without edge termination were fabricated on a SiC substrate of 4mm×4mm. The ratio of good chips to all chips (9~12 SBD) increases with increasing total thickness of sacrificial oxide grown after high temperature annealing at 1800oC for 30 s, where an SBD with a leakage current less than 1μA/cm2 at reverse voltage of –100V was defined as a good chip. We applied this process growing sacrificial oxide of 150nm after high temperature annealing to fabricate the SBD with an FLR structure designed with 600V blocking voltage on a Si-face SiC substrate. The SBD with an FLR structure through this process of 150 nm sacrificial oxide is low leakage current of less than 1μA/cm2 at reverse voltage of –100V and achieves 600V blocking voltage, however, the SBD with an FLR structure without the process of sacrificial oxide after high temperature annealing is high leakage current at reverse voltage of –100V. It is shown that this process growing sacrificial oxide after high temperature annealing is useful to fabricate an SBD with an FLR structure.

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000130-000133 ◽  
Author(s):  
Dorothee Dietz ◽  
Yusuf Celik ◽  
Andreas Goehlich ◽  
Holger Vogt ◽  
Holger Kappert

High-temperature passive electronic becomes more and more important, e.g. in the field of deep drilling, aerospace or in automobile industry. For these applications, capacitors are needed, which are able to withstand temperatures up to 300 °C, which exhibit a low leakage current at elevated temperatures, a breakdown voltage above the intended operating voltage and a high capacitive density value. In this paper, investigations of 3D-integration and atomic layer deposition (ALD) techniques to achieve these features are presented. A highly n-doped Si-substrate acts as a bottom electrode. Medium- and high-k dielectrics represent the insulator and the upper electrode consists of Ru, TiN or TiAlCN. The materials can be used at elevated temperatures. At room temperature, the leakage current is less than 10 pA/mm2 without showing a soft-breakdown up to ± 15 V, indicating the absence of Fowler-Nordheim tunneling. At 300 °C and at 3 V the leakage current amounts about 1 nA/mm2 and at 5 V a soft-breakdown is detected.


2017 ◽  
Vol 10 (12) ◽  
pp. 121002 ◽  
Author(s):  
Kazuya Hasegawa ◽  
Go Nishio ◽  
Kota Yasunishi ◽  
Nariaki Tanaka ◽  
Noriaki Murakami ◽  
...  

1993 ◽  
Vol 310 ◽  
Author(s):  
Jiyoung Kim ◽  
C. Sudhama ◽  
Rajesh Khamankar ◽  
Jack Lee

AbstractIn this work, a high-temperature deposition technique has been developed for ultra-thin sputtered PZT films for ULSI DRAM (<256Mb) storage capacitor applications. In contrast to the previously developed low-temperature (200°C) deposition, deposition at high-temperature (400°C) yields a desirable reduction in grain size of the perovskite phase. The thickness of PZT films has been reduced to less than 30nm with high charge storage density (∼30μC/cm2) and low leakage current density. An optimized 65nm PZT thin film was found to have an equivalent SiO2 thickness of 1.9Å and a leakage current density of less than 10−6 A/cm2 under 2V operation.


2005 ◽  
Vol 483-485 ◽  
pp. 953-956 ◽  
Author(s):  
Tetsuya Hayashi ◽  
Hideaki Tanaka ◽  
Yoshio Shimoida ◽  
Satoshi Tanimoto ◽  
Masakatsu Hoshi

We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.


1992 ◽  
Vol 284 ◽  
Author(s):  
Kee-Won Kwon ◽  
Chang-Seok Kang ◽  
Tai-su Park ◽  
Yong-Bin Sun ◽  
Neal Sandler ◽  
...  

ABSTRACTTa2O5 films of high reliability and low leakage current density were obtained by low temperature deposition and subsequent high temperature oxygen anneal. At higher temperatures than 410°C, growth was governed by the formation of radicals in gas phase and oxidation on the surface, while at lower temperatures by the dissociation of reactant on the surface of substrates. As a result, the films deposited at lower temperatures had undensified structures, and contained more carbon that might be a leakage current source in Ta2O5 film. During post-deposition heat treatment in 800°C oxidating ambient, carbon was removed away and silicon was diffused from the substrate into the Ta2O5 film efficiently for its as-grown porous structure. After oxygen anneal, low temperature films get denser and are crystallized to mixed phase of orthorhombic and hexagonal Ta2O5, while high temperature films crystallized to orthorhombic single phase. Ta2O5 capacitor with low temperature films showed superior leakage characteristics applicable to sub-half micron memory devices.


2021 ◽  
Vol 285 ◽  
pp. 129120
Author(s):  
Wenxin Liang ◽  
Hongfeng Zhao ◽  
Xiaoji Meng ◽  
Shaohua Fan ◽  
Qingyun Xie

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


2018 ◽  
Vol 65 (2) ◽  
pp. 680-686 ◽  
Author(s):  
Cheng-Jung Lee ◽  
Ke-Jing Lee ◽  
Yu-Chi Chang ◽  
Li-Wen Wang ◽  
Der-Wei Chou ◽  
...  

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