New Flip-Chip Interconnect Technology for High Performance and High Reliability Applications

As the current and next generation devices are embracing geometries below 28nm and requiring softer low-K dielectric isolation on very thin large silicon dies ∼ to perform a reliable die-to-package interconnect is becoming a challenge. Further, the high pressure from Cu wire bonding and high reflow temperature of conventional flip-chip bonding often results in damage of device structure. A new flip-chip bonding technology has been developed for such critical applications, and is claimed to be “damage free”. It uses soft bump made by non-full cured conductive paste on the package substrate. These soft bumps require ultra-low bonding pressure on the pad of the die. Thus the bonding process don't make any damage on ULK isolation layer. Details of the process, material sets used for such fragile device structures have been discussed. Reliability results are shared, which further ensures the robustness of this process. Finally, the cost advantage through adaptation of this process has also been elaborated.