scholarly journals Design, Modeling of Ga-As based MESFET for SRAM Cell

2020 ◽  
Vol 2 (2) ◽  
pp. 86-89
Author(s):  
Manvinder Sharma ◽  
Anuj Kumar Gupta ◽  
Dishant Khosla ◽  
Jagbir Singh Gill ◽  
Hauwa Amshi
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Temperature Tolerance ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Main Attention ◽  
Sram Cell ◽  
Conventional Cell ◽  
Result Analysis ◽  
Reduced Power Consumption

The main attention in the area of technology is given to the low power SRAM (Static random Access Memory).GaAs SRAM have been developed with great efforts which include its many advantages such as reduced power consumption and temperature tolerance. There are many limitations of conventional cell which are overcome by the design of new cell which is used to simulate SRAM. The structure of MESFET and the limitations are discussed in the paper. Further, a code in silvaco is run and simulated and the result analysis is done using tony plots.

Design of a Stable Low Power 11-T Static Random Access Memory Cell

2020 ◽  
Vol 29 (13) ◽  
pp. 2050206 ◽  
Author(s):  
Ashish Sachdeva ◽  
V. K. Tomar
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Signal To Noise ◽  
Access Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Variation Tolerance ◽  
Read Signal

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

scholarly journals Circuit Implementation, Operation, and Simulation of Multivalued Nonvolatile Static Random Access Memory Using a Resistivity Change Device

2013 ◽  
Vol 2013 ◽  
pp. 1-9
Author(s):  
Kazuya Nakayama ◽  
Akio Kitagawa
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Power Supply Voltage ◽  
Sram Cell ◽  
Variation Tolerance ◽  
Recall Operation

We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a programmable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write pulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required when using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we simulated the effect of variations in the width of the transistor of the proposed MNV-SRAM cell, the resistance of the programmable resistor, and the power supply voltage with 180 nm 3.3 V CMOS HSPICE device models.

Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability

2015 ◽  
Vol 25 (01) ◽  
pp. 1640009 ◽  
Author(s):  
Shairfe Muhammad Salahuddin ◽  
Volkan Kursun
Keyword(s):  
Power Supply ◽  
Current Flow ◽  
Supply Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Power Supply Voltage ◽  
Sram Cell ◽  
Memory Circuits

A novel six-transistor static random-access memory (6T SRAM) cell is proposed in this paper for enhancing the data stability and write ability as compared to the conventional memory circuits. Asymmetrically gate overlapped / underlapped FinFETs are employed as bitline access transistors in the proposed SRAM cell. The strength of the asymmetrical bitline access transistors are weakened during read operations. Furthermore, voltage transfer characteristics (VTCs) of cross-coupled inverters have narrower transition regions in the new SRAM cell as compared to the conventional SRAM cells. The proposed SRAM cell thereby provides stronger read data stability as compared to the conventional symmetrical SRAM cells. The strength of bitline access transistors are enhanced during write operations as the direction of current flow is reversed in the new asymmetrical SRAM cell. The power supply voltage of a selected word floats during write operations. The write voltage margin is thereby significantly increased with the proposed SRAM cell as compared to the conventional SRAM cells. The read data stability and write ability are both enhanced by up to 51.7% and 65.5%, respectively, with the proposed SRAM cell as compared to the conventional symmetrical six-FinFET SRAM cells in a 15[Formula: see text]nm FinFET technology.

scholarly journals One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Sangik Choi ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Cell Array ◽  
Access Memory ◽  
Sram Cell ◽  
The Individual

AbstractIn this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit

2005 ◽  
Vol 41 (24) ◽  
pp. 1316 ◽  
Author(s):  
Y.S. Yu ◽  
H.W. Kye ◽  
B.N. Song ◽  
S.-J. Kim ◽  
J.-B. Choi
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Single Electron ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Sram Cell ◽  
Hybrid Circuit

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

2020 ◽  
pp. 2150073 ◽  
Author(s):  
Ashish Sachdeva ◽  
V. K. Tomar
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Time ◽  
Signal To Noise ◽  
Access Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Power Delay Product

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by [Formula: see text] as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than the considered D2p11T cell. The proposed 10T cell shows [Formula: see text] and [Formula: see text] narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by [Formula: see text] as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are [Formula: see text] and [Formula: see text] lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45[Formula: see text]nm technology file has been utilized to carry out simulations.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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