New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Floating Gate ◽  
Dual Control ◽  
Switching Voltage ◽  
Voltage Range ◽  
Rail To Rail ◽  
Floating Gate Transistor ◽  
Simulation Results

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

Sub-Volt Fully Balanced Differential Difference Amplifier

2014 ◽  
Vol 24 (01) ◽  
pp. 1550005 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Spyridon Vlassis ◽  
Costas Psychalinos ◽  
Tomasz Kulej
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Voltage Range ◽  
State Variable ◽  
Low Voltage Operation ◽  
Differential Difference Amplifier ◽  
Simulation Results ◽  
State Variable Filter

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Schmitt Trigger ◽  
Floating Gate ◽  
Dual Control ◽  
Floating Gate Transistor

scholarly journals A New Rail-to-Rail Second Generation Voltage Conveyor

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1292 ◽  
Author(s):  
Barile ◽  
Stornelli ◽  
Ferri ◽  
Safari ◽  
D’Amico
Keyword(s):  
Second Generation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Voltage Range ◽  
Class Ab ◽  
Rail To Rail ◽  
Total Power Consumption ◽  
Voltage Swing

In this paper, a novel low voltage low power CMOS second generation voltage conveyor (VCII) with an improved voltage range at both the X and Z terminals is presented. The proposed VCII is formed by a current buffer based on a class AB regulated common-gate stage and a modified rail-to-rail voltage buffer. Spice simulation results using LFoundry 0.15 μm low-Vth CMOS technology with a ±0.9 V supply voltage are provided to demonstrate the validity of the designed circuit. Thanks to the class AB behavior, from a bias current of 10 µA, the proposed VCII is capable of driving 0.5 mA on the X terminal, with a total power consumption of 120 µW. The allowed voltage swing on the Z terminal is at least equal to ±0.83 V, while on the X terminals it is ±0.72 V. Both DC and AC voltage and current gains are provided, and time domain simulations, where the voltage conveyor is used as a transimpedance amplifier (TIA), are also presented. A final table that summarizes the main features of the circuit, comparing them with the literature, is also given.

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

A High-Linear CMOS Down Conversion Mixer Using Adjusting the Second and Third-Order Harmonic in Transconductance Stage

2014 ◽  
Vol 24 (01) ◽  
pp. 1550002 ◽  
Author(s):  
Mina Amiri ◽  
Adib Abrishamifar
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Conversion Gain ◽  
Third Order ◽  
Cmos Mixer ◽  
Simulation Results ◽  
Down Conversion ◽  
Pmos Transistor

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.

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