scholarly journals Design of a LNA in the frequency band 1.8-2.2GHz in 0.13μm CMOS Technology

2005 ◽  
Vol 3 ◽  
pp. 299-303
Author(s):  
E. Di Gioia ◽  
C. Hermann ◽  
H. Klar
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Operating Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
High Gain ◽  
Low Noise ◽  
Noise Amplifier ◽  
Low Supply Voltage

Abstract. The subject of this work is a low noise amplifier (LNA), operating in the frequency range 1.8-2.1GHz. The CMOS 0.13μm technology is used in respect to the low cost of the final device. Among the specifications, a variable gain and an adjustable working frequency are required. In particular, four different working modes are provided: 1.8, 1.9 and 2.1GHz high gain and 2.1GHz low gain. The amplifier is designed to be used as first stage of a receiver for mobile telephony. For this reason low power consumption is taken into consideration (low supply voltage and low drain currents). A simple digital circuit, integrated on-chip, is used to select the operating mode of the LNA by means of two input pins. A Noise figure of 1dB is obtained with a supply voltage of 0.8V.

scholarly journals A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

2019 ◽  
Vol 14 (2) ◽  
pp. 555
Author(s):  
S.A.Z. Murad ◽  
A. F. Hasan ◽  
A. Azizan ◽  
A. Harun ◽  
J. Karim
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Notch Filter ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Common Source ◽  
Noise Amplifier

<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

scholarly journals Design and implementation of a broad-band high gain low noise amplifier for 3G/4G applications

2021 ◽  
Vol 23 (2) ◽  
pp. 725
Author(s):  
Ahmed M. Abdelmonem ◽  
Ahmed S. I. Amar ◽  
Amir Almslmany ◽  
Ibrahim L. Abdalla ◽  
Fathi A. Farag
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Broad Band ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Matching Network ◽  
Noise Amplifier

The main aim of the paper is designing and implementing a broadband low-noise-amplifier (LNA) based on compensated matching network techniquein order to get high stable gain, low noise figure, low cost and smaller sizefor 3G/4G communication system applications at 2 GHz with bandwidth 600MHz. The Advanced Design System simulates the proposed circuit (ADS).The implementation was done with a class A bias circuit and a low noise transistor BFU 730F with a lower Noise Figure (NFmin) 0.62 dB. Collectorcurrent is measured to be 5.8mA and base current is 19.1μA with a supply voltage of 2.25V. The new design proposed a (NFmin) of 0.62 dB with a 17.8dB high stable amplifier gain. The microstrip lines (MSL) and compensated matching network techniques were used to improve the LNA’s stability and achieve a good result. The LNA board is implemented and assembled on the FR4 botton layer material. The results are virtually non existence equivalent between the simulated and the measured results.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

2019 ◽  
Vol 33 (23) ◽  
pp. 1950280
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Pengfei Yue ◽  
Lei Luo ◽  
Xiaodong He ◽  
...  
Keyword(s):  
Noise Figure ◽  
Nonlinear Coefficient ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Third Order ◽  
Input Matching ◽  
Third Stage ◽  
Protection Circuits ◽  
Noise Amplifier

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

scholarly journals Design and Implementation of Low Noise Amplifier At 60ghz using Current Mirror Feedback

2019 ◽  
Vol 8 (9S3) ◽  
pp. 249-254
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Single Stage ◽  
Common Source ◽  
Small Signal ◽  
Total Size ◽  
Noise Amplifier

This discourse used 45nm CMOS technology to design a Low noise amplifier for a Noise figure < 2dB and gain greater than 13dB at the 60GHz unlicensed band of frequency. A single stage, primary cascode LNA is modeled and its small signal model is analyzed. Common source structure is hired in the driver stage to escalate the output power with single stage contours. To enhance small signal gain, simple active transistor feedback and cascode feedback configurations are designed and appended to the basic LNA. In addition to this, current re-use inductor is designed and added to the cascode amplifier which is deliberated to give low power and low noise figure. Small signal analysis of simple active transistor feedback and current re-use inductor has been presented. The measurement results indicated that the input match and the output gain at 60GHz achieves -8dB and 13dB respectively with the supply voltage of 900mV. The frequency response obtained is a narrow band response with 6GHz of bandwidth. The circuit is simulated by Cadence Virtuoso tool. The layout of the related circuit is drawn by means of the Virtuoso Layout editor with total size of 0.1699μm2.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

2017 ◽  
Vol 27 (03) ◽  
pp. 1850047
Author(s):  
Xin Zhang ◽  
Chunhua Wang ◽  
Yichuang Sun ◽  
Haijun Peng
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Low Noise ◽  
Ultra Wideband ◽  
Oxide Semiconductor ◽  
High Linearity ◽  
Low Supply Voltage

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

scholarly journals Linearity improvement of differential CMOS low noise amplifier

2019 ◽  
Vol 14 (1) ◽  
pp. 407
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Linearity Improvement ◽  
Noise Amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

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