scholarly journals Design and implementation of a broad-band high gain low noise amplifier for 3G/4G applications

2021 ◽  
Vol 23 (2) ◽  
pp. 725
Author(s):  
Ahmed M. Abdelmonem ◽  
Ahmed S. I. Amar ◽  
Amir Almslmany ◽  
Ibrahim L. Abdalla ◽  
Fathi A. Farag
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Broad Band ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Matching Network ◽  
Noise Amplifier

The main aim of the paper is designing and implementing a broadband low-noise-amplifier (LNA) based on compensated matching network techniquein order to get high stable gain, low noise figure, low cost and smaller sizefor 3G/4G communication system applications at 2 GHz with bandwidth 600MHz. The Advanced Design System simulates the proposed circuit (ADS).The implementation was done with a class A bias circuit and a low noise transistor BFU 730F with a lower Noise Figure (NFmin) 0.62 dB. Collectorcurrent is measured to be 5.8mA and base current is 19.1μA with a supply voltage of 2.25V. The new design proposed a (NFmin) of 0.62 dB with a 17.8dB high stable amplifier gain. The microstrip lines (MSL) and compensated matching network techniques were used to improve the LNA’s stability and achieve a good result. The LNA board is implemented and assembled on the FR4 botton layer material. The results are virtually non existence equivalent between the simulated and the measured results.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

Concurrent Multi-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (06) ◽  
pp. 1750104 ◽  
Author(s):  
Ramya ◽  
T. Rama Rao ◽  
Revathi Venkataraman
Keyword(s):  
Noise Figure ◽  
Transformation Method ◽  
High Gain ◽  
Wide Frequency Range ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Vehicular Communication ◽  
Matching Network ◽  
Noise Amplifier ◽  
Multi Band

With rapid expansions of wireless communications, requirements for transceivers that support concurrent multiple services are continuously increasing and demanding design of a concurrent low-noise amplifier (LNA) with low noise figure (NF), high gain, and high linearity over a wide frequency range for various wireless applications. The proposed work focuses on a concurrent multi-band LNA that works at navigational frequencies, namely, of 1.2[Formula: see text]GHz and 1.5[Formula: see text]GHz, wireless communication frequencies, namely, of 2.45[Formula: see text]GHz and 3.3[Formula: see text]GHz, dedicated short range communication (DSRC) frequency of 5.8[Formula: see text]GHz for the vehicular communication applications. This circuit has a distinct input matching network which resonates at all desired five frequency bands and is achieved by adapting frequency transformation method. To accomplish simultaneous reception of the desired penta-band, the output matching is designed with simple LC matching network with the aid of load-pull methodology.

scholarly journals A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

2019 ◽  
Vol 14 (2) ◽  
pp. 555
Author(s):  
S.A.Z. Murad ◽  
A. F. Hasan ◽  
A. Azizan ◽  
A. Harun ◽  
J. Karim
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Notch Filter ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Common Source ◽  
Noise Amplifier

<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

scholarly journals Design of a LNA in the frequency band 1.8-2.2GHz in 0.13μm CMOS Technology

2005 ◽  
Vol 3 ◽  
pp. 299-303
Author(s):  
E. Di Gioia ◽  
C. Hermann ◽  
H. Klar
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Operating Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
High Gain ◽  
Low Noise ◽  
Noise Amplifier ◽  
Low Supply Voltage

Abstract. The subject of this work is a low noise amplifier (LNA), operating in the frequency range 1.8-2.1GHz. The CMOS 0.13μm technology is used in respect to the low cost of the final device. Among the specifications, a variable gain and an adjustable working frequency are required. In particular, four different working modes are provided: 1.8, 1.9 and 2.1GHz high gain and 2.1GHz low gain. The amplifier is designed to be used as first stage of a receiver for mobile telephony. For this reason low power consumption is taken into consideration (low supply voltage and low drain currents). A simple digital circuit, integrated on-chip, is used to select the operating mode of the LNA by means of two input pins. A Noise figure of 1dB is obtained with a supply voltage of 0.8V.

scholarly journals UWB-MMIC Matrix Distributed Low Noise Amplifier

Proceedings ◽  
2020 ◽  
Vol 63 (1) ◽  
pp. 52
Author(s):  
Moustapha El Bakkali ◽  
Said Elkhaldi ◽  
Intissar Hamzi ◽  
Abdelhafid Marroun ◽  
Naima Amar Touhami
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Design System ◽  
High Electron ◽  
Power Gain ◽  
Noise Amplifier

In this paper, a 3.1–11 GHz ultra-wideband low noise amplifier with low noise figure, high power gain S21, low reverse gain S12, and high linearity using the OMMIC ED02AH process, which employs a 0.18 μm Pseudomorphic High Electron Mobility Transistor is presented. This Low Noise Amplifier (LNA) was designed with the Advanced Design System simulator in distributed matrix architecture. For the low noise amplifier, four stages were used obtaining a good input/output matching. An average power gain S21 of 11.6 dB with a gain ripple of ±0.6 dB and excellent noise figure of 3.55 to 4.25 dB is obtained in required band with a power dissipation of 48 mW under a supply voltage of 2 V. The input compression point 1 dB and third-order input intercept point are −1.5 and 23 dBm respectively. The core layout size is 1.8 × 1.2 mm2.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

The Special Research on a Low Noise Amplifier

2012 ◽  
Vol 605-607 ◽  
pp. 2057-2061
Author(s):  
Xin Yin ◽  
Yi Yao ◽  
Jin Ling Jia
Keyword(s):  
Wireless Local Area Network ◽  
Local Area Network ◽  
Noise Figure ◽  
Design Method ◽  
Local Area ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Area Network ◽  
Noise Amplifier

This paper studies a low noise amplifier design method for 5.8G wireless local area network. Using the software of designing RF circuit ADS(Advanced Design System) and Avago Technologies’s ATF-36077,we designed a three-cascade LNA. In 5.725G~5.85GHz range, noise figure less than 0.5dB, more than 30dB gain, input and output standing wave ratio less than 1.3dB.The LNA meet the design requirements.

scholarly journals Design and Analysis High Gain PHEMT LNA for Wireless Application at 5.8 GHz

2015 ◽  
Vol 5 (3) ◽  
pp. 611
Author(s):  
Kamil Pongot ◽  
Abdul Rani Othman ◽  
Zahriladha Zakaria ◽  
Mohamad Kadim Suaidi ◽  
Abdul Hamid Hamidon ◽  
...  
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Output Terminal ◽  
Wireless Application ◽  
Noise Amplifier ◽  
The Stability ◽  
Inductive Generation

This research present a design of a higher  gain (66.38dB) for PHEMT LNA  using an inductive drain feedback technique for wireless application at 5.8GHz. The amplifier it is implemented using PHEMT FHX76LP transistor devices.  The designed circuit is simulated with  Ansoft Designer SV.  The LNA was designed using  T-network as a matching technique was used at the input and output terminal,  inductive generation to the source and an inductive drain feedback. The  low noise amplifier (LNA) using lumped-component provides a noise figure 0.64 dB and a gain (S<sub>21</sub>) of 68.94 dB. The output reflection (S<sub>22</sub>), input reflection (S<sub>11</sub>) and return loss (S<sub>12</sub>) are -17.37 dB, -15.77 dB and -88.39 dB respectively. The measurement shows the  stability was at  4.54 and 3-dB bandwidth of 1.72 GHz. While, the  low noise amplifier (LNA) using  Murata manufactured component provides a noise figure 0.60 dB and a gain (S<sub>21</sub>) of 66.38 dB. The output reflection (S<sub>22</sub>), input reflection (S<sub>11</sub>) and return loss (S<sub>12</sub>) are -13.88 dB, -12.41 dB and -89.90 dB respectively. The measurement shows the  stability was at  6.81 and 3-dB bandwidth of 1.70 GHz. The input sensitivity more than -80 dBm  exceeded the standards required by IEEE 802.16.

scholarly journals Single Stage 180nm CMOS Low Noise Amplifier Topologies and Optimization Algorithms for S Band Frequency

2019 ◽  
Vol 8 (3) ◽  
pp. 152-157 ◽  
Keyword(s):  
Noise Figure ◽  
Optimization Algorithms ◽  
Satellite System ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Active Device ◽  
Band Frequency ◽  
Noise Amplifier

Low Noise Amplifier (LNA) plays an important role in radio receivers. It mainly determines the system noise and intermodulation behavior of overall receiver. LNA design is more challenging as it requires high gain, low noise figure, good input and output matching and unconditional stability. Further, designing a Low noise Amplifier requires active device selection, amplifier topology, optimization algorithms for superlative results. Hence this paper presents performance analysis of CMOS LNA based on different topologies and optimization algorithms for 180nm RF CMOS design in S band frequency. Here the best results, various limitations in each topology are reviewed and required specifications are determined in each designing. Further this best topology is used for designing LNA circuit which could be used in Indian Regional Navigation Satellite System (IRNSS) applications in dual band frequency.

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