scholarly journals A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER

2018 ◽  
Vol 14 (1) ◽  
pp. 64-68
Author(s):  
Lianly Rompis
Keyword(s):  
Simple Form ◽  
Basic Concept ◽  
Digital Circuit ◽  
Truth Table ◽  
Shift Register ◽  
Logic Simulation ◽  
Flip Flop ◽  
Standard Format ◽  
Counter Circuit ◽  
The Right

Mostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, using shift register and encoder, which is easier to applied and the sequence of this counter can be managed randomly. The methodology being used for this research is mainly tounderstand the basic concept and combine the functions of shift register and encoder, to derive a new and simple form of designing a random counter. Using an Electronics Workbench software, the outputs are shown in logic simulation.

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

2011 ◽  
Vol E94-A (12) ◽  
pp. 2669-2675 ◽  
Author(s):  
Chikara HAMANAKA ◽  
Ryosuke YAMAMOTO ◽  
Jun FURUTA ◽  
Kanto KUBOTA ◽  
Kazutoshi KOBAYASHI ◽  
...  
Keyword(s):  
Shift Register ◽  
Flip Flop ◽  
Variation Tolerance ◽  
Modular Redundancy

Butterfly interconnection network: design of multiplier, flip-flop, and shift register

1994 ◽  
Vol 33 (8) ◽  
pp. 1457 ◽  
Author(s):  
Khan M. Iftekharuddin ◽  
Mohammad A. Karim
Keyword(s):  
Network Design ◽  
Interconnection Network ◽  
Shift Register ◽  
Flip Flop

scholarly journals BUSINESS RISK ATAUKAH HUMAN ERROR

2018 ◽  
Vol 16 (1) ◽  
pp. 51-64
Author(s):  
Miftachul Ulum
Keyword(s):  
Standard Deviation ◽  
Basic Concept ◽  
Human Error ◽  
Business Risk ◽  
Human Reason ◽  
The Right

Abstract: In every decision made by the business, it is always confronted with an uncertainty that we know as risks. Stakeholders are those who influence or will be influenced by the decision. Statistically risk can be formulated as a deviation. The magnitude of risk can be measured by variance (?2) or standard deviation (?). Through prudential principles, the types and forms of risk can be avoided or minimized. The carelessness is a factor of human error which is a factor beyond human reason. Humans are only able to put the basic concept of prudence in making decisions but all the terms of haqiqi will be the right of the Almighty.  Abstraksi : Setiap pengambilan keputusan yang dilakukan oleh pelaku bisnis selalu dihadapkan  pada suatu ketidakpastian yang kita kenal dengan risiko. Stakeholder sebagai pemangku kepentingan merupakan pihak yang mempengaruhi atau yang akan dipengaruhi  keputusan tersebut. Secara statistik risiko dapat dirumuskan sebagai penyimpangan, besarnya risiko dapat diukur dengan variance (?2) atau standar deviasi. Melalui prinsip kehati-hatian jenis dan bentuk risiko dapat dihindari atau bahkan dapat diminimalkan. Kelalaian adalah   merupakan suatu  faktor yang diluar nalar manusia. Manusia hanya meletakkan konsep dasar kehati-hatian dalam mengambil keputusan namun ketentuan secara haqiqi menjadi hak Yang Maha Kuasa.

scholarly journals Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Electronics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 92 ◽  
Author(s):  
Mohammad Badal ◽  
Mamun Reaz ◽  
Zinah Jalil ◽  
Mohammad Bhuiyan
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Shift Register ◽  
Cmos Process ◽  
Flip Flop ◽  
Rfid Tag

scholarly journals Novel Low-Complexity and Low-Power Flip-Flop Design

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 783
Author(s):  
Jin-Fa Lin ◽  
Zheng-Jie Hong ◽  
Chang-Ming Tsai ◽  
Bo-Cheng Wu ◽  
Shao-Wei Yu
Keyword(s):  
Low Power ◽  
Average Power ◽  
Circuit Complexity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Flip Flop ◽  
Chip Area

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

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