scholarly journals Metal Gate Electrode and High-Dielectrics for Sub-32nm Bulk CMOS Technology: Integrating Lanthanum Oxide Capping Layer for Low Threshold-Voltage Devices Application

Author(s):  
HongYu Yu
2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.


2006 ◽  
Vol 83 (11-12) ◽  
pp. 2516-2521
Author(s):  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang

2006 ◽  
Vol 917 ◽  
Author(s):  
Raghunath Singanamalla ◽  
Judit Lisoni ◽  
Isabelle Ferain ◽  
Olivier Richard ◽  
Laure Carbonell ◽  
...  

AbstractThe electrical and material characterization of Ti(C)N deposited by metal organic chemical vapor deposition (MOCVD) technique, as metal gate electrode for advanced CMOS technology is investigated. The effects of the plasma treatment, post anneal treatment and the thickness variation of the Ti(C)N film on the flat band voltage (VFB) and effective work function (WF) of the Poly-Si/Ti(C)N/SiO2 Poly-Si/Ti(C)N/SiO2 gate stack s are reported. We found that both the in-situ plasma treatment and post anneal treatment help in reducing the carbon content (organic) in the film making it more metallic compared to the as-deposited films. However, the post anneal treatment was found to be a better option for getting rid of hydrocarbons as compared to plasma treatment from the gate dielectric integrity point of view. The thickness variation of post annealed Ti(C)N film ranged from 2.5 nm to 10 nm lead to WF shift of upto ~350 mV for both Poly-Si/Ti(C)N/SiO2 and Poly-Si/Ti(C)N/HfO2 gate stacks.


2011 ◽  
Vol 9 (8) ◽  
pp. 082301-82304
Author(s):  
董赞 Zan Dong ◽  
王伟 Wei Wang ◽  
黄北举 Beiju Huang ◽  
张旭 Xu Zhang ◽  
关宁 Ning Guan ◽  
...  

2006 ◽  
Vol 45 (8A) ◽  
pp. 6225-6230 ◽  
Author(s):  
Masaru Kadoshima ◽  
Toshihide Nabatame ◽  
Kunihiko Iwamoto ◽  
Nobuyuki Mise ◽  
Hiroyuki Ota ◽  
...  

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