Compatibility of HfxTayN metal gate electrode with HfOxNy gate dielectric for advanced CMOS technology

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2516-2521
Author(s):  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
Tien-Ko Wang
2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.


2001 ◽  
Vol 22 (5) ◽  
pp. 227-229 ◽  
Author(s):  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
P. Ranade ◽  
H. Takeuchi ◽  
K.J. Yang ◽  
...  

2006 ◽  
Vol 917 ◽  
Author(s):  
Raghunath Singanamalla ◽  
Judit Lisoni ◽  
Isabelle Ferain ◽  
Olivier Richard ◽  
Laure Carbonell ◽  
...  

AbstractThe electrical and material characterization of Ti(C)N deposited by metal organic chemical vapor deposition (MOCVD) technique, as metal gate electrode for advanced CMOS technology is investigated. The effects of the plasma treatment, post anneal treatment and the thickness variation of the Ti(C)N film on the flat band voltage (VFB) and effective work function (WF) of the Poly-Si/Ti(C)N/SiO2 Poly-Si/Ti(C)N/SiO2 gate stack s are reported. We found that both the in-situ plasma treatment and post anneal treatment help in reducing the carbon content (organic) in the film making it more metallic compared to the as-deposited films. However, the post anneal treatment was found to be a better option for getting rid of hydrocarbons as compared to plasma treatment from the gate dielectric integrity point of view. The thickness variation of post annealed Ti(C)N film ranged from 2.5 nm to 10 nm lead to WF shift of upto ~350 mV for both Poly-Si/Ti(C)N/SiO2 and Poly-Si/Ti(C)N/HfO2 gate stacks.


2012 ◽  
Vol 195 ◽  
pp. 13-16 ◽  
Author(s):  
Farid Sebaai ◽  
Anabela Veloso ◽  
Hiroaki Takahashi ◽  
Antoine Pacco ◽  
Martine Claes ◽  
...  

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).


2019 ◽  
Vol 2 (1) ◽  
pp. 41-48
Author(s):  
Rosa María Luna-Sánchez ◽  
Ignacio González-Martínez

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Wu-Te Weng ◽  
Yao-Jen Lee ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.


2004 ◽  
Vol 48 (10-11) ◽  
pp. 1987-1992 ◽  
Author(s):  
Shiyang Zhu ◽  
H.Y. Yu ◽  
J.D. Chen ◽  
S.J. Whang ◽  
J.H. Chen ◽  
...  

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