scholarly journals Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development

2018 ◽  
Author(s):  
Steven H. Voldman
Keyword(s):  
Electrostatic Discharge ◽  
Latch Up

scholarly journals Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1469 ◽  
Author(s):  
Po-Lin Lin ◽  
Shen-Li Chen ◽  
Sheng-Kai Fan
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
Breakdown Voltage ◽  
Electrostatic Discharge ◽  
Reference Group ◽  
Lateral Diffusion ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Field Oxide ◽  
Latch Up

Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

A Novel High Latch-Up Immunity Electrostatic Discharge Protection Device for Power Rail in High-Voltage ICs

2016 ◽  
Vol 16 (2) ◽  
pp. 266-268
Author(s):  
Chunwei Zhang ◽  
Siyang Liu ◽  
Kaikai Xu ◽  
Jiaxing Wei ◽  
Ran Ye ◽  
...  
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Protection Device ◽  
Latch Up

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

2004 ◽  
Vol 39 (10) ◽  
pp. 1778-1782 ◽  
Author(s):  
D. Tremouilles ◽  
M. Bafleur ◽  
G. Bertrand ◽  
N. Nolhier ◽  
N. Mauran ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Design Guidelines ◽  
Protection Scheme ◽  
Esd Protection ◽  
Latch Up

Electric Shock and Safety Evaluation for Electrostatic Discharge from Human

2017 ◽  
Vol 137 (4) ◽  
pp. 229-235
Author(s):  
Yoshinori Taka ◽  
Akimasa Hirata ◽  
Kenichi Yamazaki ◽  
Osamu Fujiwara
Keyword(s):  
Electric Shock ◽  
Electrostatic Discharge ◽  
Safety Evaluation

Latch-Up Induced Slit Voiding in Aluminum Metal Lines

1999 ◽  
Author(s):  
Chunyu Zhang ◽  
Lakshmi Vedula ◽  
Shekhar Khandekar
Keyword(s):  
High Temperature ◽  
Line Width ◽  
Fold Increase ◽  
Metal Line ◽  
Operating Life ◽  
Mixed Signal ◽  
Aluminum Metal ◽  
Temperature Operating ◽  
Latch Up

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

Conversion of a D-Mode FET to an E-Mode FET via Electrostatic Discharge in a GaAs Power Amplifier Duplexer Module

2013 ◽  
Author(s):  
Rose Emergo ◽  
Steve Brockett
Keyword(s):  
Cross Section ◽  
Power Amplifier ◽  
Electrostatic Discharge ◽  
Fault Isolation ◽  
Design Change ◽  
Eds Analysis ◽  
Defect Simulation

Abstract This paper outlines the systematic isolation of an electrostatic discharge defect on a depletion-mode FET. Topics covered are fault isolation, FIB-STEM cross-section and EDS analysis, and defect simulation. Multiple GaAs PA devices were submitted for analysis after failing different reliability stresses. Fault isolation revealed ESD damage on a DFET connected to the VMODE0 pin. Simulation of the failure showed that, most likely, the defect was caused by CDM stress. A design change of inserting a resistor between the VMODE0 pin and the DFET made the device more robust against CDM stress.

A Methodology for Characterizing System-Level ESD Sensitivity

2004 ◽  
Author(s):  
Marie-Pascale Chagny ◽  
John A. Naoum
Keyword(s):  
Electrostatic Discharge ◽  
Computer Systems ◽  
Electronic Equipment ◽  
Experimental Methodology ◽  
Computer Users ◽  
System Level ◽  
Permanent Damage ◽  
Design Improvement ◽  
Desktop Computers

Abstract Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.

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