scholarly journals Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1469 ◽  
Author(s):  
Po-Lin Lin ◽  
Shen-Li Chen ◽  
Sheng-Kai Fan
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
Breakdown Voltage ◽  
Electrostatic Discharge ◽  
Reference Group ◽  
Lateral Diffusion ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Field Oxide ◽  
Latch Up

Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

A New Slope SOI-LDMOS High-Voltage Power Device

2012 ◽  
Vol 236-237 ◽  
pp. 797-800
Author(s):  
Xiao Ming Yang ◽  
Yu Cai ◽  
Tian Qian Li
Keyword(s):  
Oxide Layer ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Power Device ◽  
Drift Region ◽  
Electrical Field ◽  
New Device ◽  
Buried Oxide ◽  
Drain Electrode ◽  
Surface Electric Field

A slope SOI-LDMOS power device is proposed for high-voltage. When a positive bais is applied to the drain electrode, holes are induced and astricted by the slope buried oxide layer. So a high density positive charge layer is formed on the buried oxide layer. The electrical field in the buried oxide is improved as well as vertical breakdown voltage by the layer. Because the thickness of the drift region linearly increases from the source to the drain, the surface electric field is optimized, resulting in increase of lateral breakdown voltage. In this paper, the electric characteristics of the new device are simulated by Medici softerware. The result is shown that above 600 V breakdown voltage is obtained at 1μm thick buried oxide layer. The breakdown voltage is higher by three times than that of conventional SOI LDMOS.

scholarly journals Analytical Breakdown Voltage Model for Partial SOI-LDMOS Transistor with Buried Oxide Step Structure

2021 ◽  
Author(s):  
Jagamohan Sahoo ◽  
Rajat Mahapatra
Keyword(s):  
Electric Field ◽  
Analytical Model ◽  
Breakdown Voltage ◽  
Point Of View ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Design Parameters ◽  
Drift Region ◽  
Two Dimensional ◽  
The Impact

Abstract We have developed a simple physics-based two-dimensional analytical Off-state breakdown voltage model of a PBOSS Silicon-On-Insulator Lateral Diffused Metal Oxide Semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson’s equation. The electric field at the Si-SiO2 surface is modified by creating additional electric field peaks due to the presence of the PBOSS structure. The uniformly distributed electric field results in improving the breakdown voltage. Further, the breakdown voltage is analytically obtained via critical electric field concept to quantify the breakdown characteristic. The model exploits the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by the results obtained from ATLAS two dimensional simulations. The analytical model is of the high potential from a physical and mathematical point of view to design high voltage SOI-LDMOS transistors for power switching applications.

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

2015 ◽  
Vol 1096 ◽  
pp. 514-519
Author(s):  
Yue Hu ◽  
Hao Wang ◽  
De Wen Wang ◽  
Cai Xia Du ◽  
Miao Miao Ma ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Impurity Atoms ◽  
Surface Field ◽  
Field Peak ◽  
Effect Transistor

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

Drain Side N+ Layout Manners ("npnpn" Arranged-Type) on ESD Robustness in the 60-V pLDMOS-SCR

2017 ◽  
Vol 870 ◽  
pp. 401-406
Author(s):  
Shen Li Chen ◽  
Yu Ting Huang ◽  
Chih Hung Yang ◽  
Chih Ying Yen ◽  
Kuei Jyun Chen ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Breakdown Voltage ◽  
Electrostatic Discharge ◽  
Reference Group ◽  
Type Structure ◽  
Experimental Results ◽  
Drain Side

Electrostatic-discharge (ESD) immunity measurements of different layout manners in the drain-side of HV pLDMOS devices are investigated in this paper. Here, eleven kinds of drain-side "npnpn" arranged-types of pLDMOS-SCR parasitic structure are used to evaluate the layout impacts on ESD robustness. In this study, at first the layout type of N+ region is continuous extended into the drain-side P+ cathode. Secondly, the layout type of N+ region is modulated by some discrete-distributed areas in the drain-side. From the experimental results, we can find that the ESD capability of the continuous extended and discrete distributed in the drain-side can be promoted, where all of the secondary breakdown current (It2) values can be achieved 7 A. However, the discrete-distributed layout type has higher breakdown voltage (VBK) than that of the reference group (the pure none modulated pLDMOS-SCR npnpn-type structure). Therefore, the discrete-distributed layout types show good electrical properties and reliability immunities.

scholarly journals New Power MOSFET with Beyond-1D-Limit RSP-BV Trade-Off and Superior Reverse Recovery Characteristics

Materials ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2581
Author(s):  
Meng Zhang ◽  
Baikui Li ◽  
Jin Wei
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Power Switching ◽  
Deep Trench ◽  
Trade Off ◽  
Power Mosfet ◽  
P Bodies ◽  
Recovery Performance

The application of conventional power metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the famous one-dimensional “silicon limit” (1D-limit) in the trade-off relationship between specific on-resistance (RSP) and breakdown voltage (BV). In this paper, a new power MOSFET architecture is proposed to achieve a beyond-1D-limit RSP-BV trade-off. Numerical TCAD (technology computer-aided design) simulations were carried out to comparatively study the proposed MOSFET, the conventional power MOSFET, and the superjunction MOSFET. All the devices were designed with the same breakdown voltage of ~550 V. The proposed MOSFET features a deep trench between neighboring p-bodies and multiple p-islands located at the sidewall and bottom of the trench. The proposed MOSFET allows a high doping concentration in the drift region, which significantly reduces its RSP compared to the conventional power MOSFET. The multiple p-islands split the electric field into multiple peaks and help the proposed MOSFET maintain a similar breakdown voltage to the conventional power MOSFET with the same drift region thickness. Another famous device technology, the superjunction MOSFET (SJ-MOSFET), also breaks the 1D-limit. However, the SJ-MOSFET suffers a snappy reverse recovery performance, which is a notorious drawback of SJ-MOSFET and limits the range of its application. On the contrary, the proposed MOSFET presents a superior reverse recovery performance and can be used in various power switching applications where hard commutation is required.

scholarly journals ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 178
Author(s):  
Shi-Zhe Hong ◽  
Shen-Li Chen
Keyword(s):  
Integrated Circuits ◽  
Electrostatic Discharge ◽  
Schottky Diodes ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Good Strategy ◽  
Fabrication Cost ◽  
Esd Protection ◽  
Drain Electrode ◽  
Length Reduction

Electrostatic discharge (ESD) events can severely damage miniature components. Therefore, ESD protection is critical in integrated circuits. In this study, drain-electrode-embedded horizontal Schottky diode contact modulation and Schottky length reduction modulation were performed on a high-voltage 60-V n-channel laterally diffused metal-oxide–semiconductor transistor (nLDMOS) element. The effect of the on-voltage characteristics of cascade Schottky diodes on ESD protection was investigated. By using a transmission-line pulse tester, the trigger voltage, holding voltage, and secondary breakdown current (It2) of the nLDMOS element were determined using the I–V characteristic. As the N+ area was gradually replaced by the parasitic Schottky area at the drain electrode, an equivalent circuit of series Schottky diodes formed, which increased the on-resistance. The larger the Schottky area was the higher the It2 value was. This characteristic can considerably improve the ESD immunity of nLDMOS components (highest improvement of 104%). This is a good strategy for improving ESD reliability without increasing the production steps and fabrication cost.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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