scholarly journals Operational Transconductance Amplifier in 350nm CMOS technology

2015 ◽  
Vol 19 (1) ◽  
pp. 32
Author(s):  
Dejan D. Mirković ◽  
Predrag M. Petković ◽  
Ilija Dimitrijević ◽  
Igor Mirčić
Keyword(s):  
Cmos Technology ◽  
Open Loop ◽  
Switched Capacitor ◽  
Loop Gain ◽  
Operational Transconductance Amplifier ◽  
Mixed Signal ◽  
Switched Capacitor Circuits ◽  
Transconductance Amplifier ◽  
Technology Process ◽  
Level Design

This paper presents transistor level design ofoperational transconductance amplifier in CMOS technology.Custom designed, circuit is to be built-in into the mixed-signal,switched capacitor circuit. Amplifier targets relatively high slewrateand moderate open loop gain with megahertz order gainbandwidth.Adopted architecture is discussed appreciatingapplication in switched capacitor circuits. Circuit behavior isexamined through set of simulations. Obtained results confirmeddesired behavior. Target technology process is TSMC 350nm.

A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI

2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000083-000088
Author(s):  
C. Su ◽  
B. J. Blalock ◽  
S. K. Islam ◽  
L. Zuo ◽  
L. M. Tolbert
Keyword(s):  
High Temperature ◽  
Analog Circuits ◽  
Flicker Noise ◽  
Data Converters ◽  
Open Loop ◽  
Automotive Electronics ◽  
Operational Transconductance Amplifier ◽  
Linear Regulator ◽  
Transconductance Amplifier ◽  
Folded Cascode

The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI processes offer several orders of magnitude smaller junction leakage current than bulk-CMOS processes at temperatures beyond 150°C. This amplifier is designed for a high temperature linear voltage regulator; the higher open-loop gain of this amplifier will enhance the overall performance of a linear regulator. In addition, the lower current consumption of the OTA is critical for improving the current efficiency of the linear regulator and reducing the power dissipation at elevated temperature. A PMOS input pair folded cascode OTA topology had been selected in this work, PMOS input pair offers wider ICMR (input common-mode range) and empirically lower flicker noise compared to its NMOS counterpart. By cascoding current mirror load at the output node, the folded cascode OTA obtains higher voltage gain than the symmetrical OTA topology. The PSRR (power supply rejection ratio) is also improved. A on-chip temperature stable current reference is employed to bias the amplifier. The amplifier consumes less than 65μA bias current at 175°C. The core layout area of the amplifier is 0.16mm2 (400 μm × 400 μm).

TIME MARKER GENERATOR USING OPERATIONAL TRANSCONDUCTANE AMPLIFIER

2015 ◽  
Vol 76 (1) ◽  
Author(s):  
Avireni Srinivasulu ◽  
V. Tejaswini ◽  
T. Pitchaiah
Keyword(s):  
Sine Wave ◽  
Experimental Results ◽  
Model Parameters ◽  
Operational Transconductance Amplifier ◽  
Passive Components ◽  
Time Marker ◽  
Square Wave ◽  
Transconductance Amplifier ◽  
Technology Process ◽  
Wave Converter

This letter introduces time marker generator (TMG) using operational transconductance amplifier (OTA). It is composed of comparator (i.e. sine wave to square wave converter), integrator and clipper. The performance of the proposed circuit is examined using Cadence and the model parameters of a 180 nm technology process.  Later, the circuit was built with commercially available OTA (LM 13600), passive components used externally and tested at the outputs of comparator, integrator and clipper. Simulations and experimental results are shown that verify the proposed circuit of time marker generator.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

2012 ◽  
Vol 433-440 ◽  
pp. 5727-5732
Author(s):  
Jun Han ◽  
Wei Dong Wang
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Optimization Technique ◽  
Cmos Technology ◽  
Switched Capacitor ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
A Chain

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

scholarly journals Design and analysis of current mirror OTA in 45 nm and 90 nm CMOS technology for bio-medical application

2020 ◽  
Vol 9 (1) ◽  
pp. 221-228
Author(s):  
Wan Mohammad Ehsan Aiman Wan Jusoh ◽  
Siti Hawa Ruslan
Keyword(s):  
Detection System ◽  
Complementary Metal Oxide Semiconductor ◽  
Medical Application ◽  
Cmos Technology ◽  
Open Loop ◽  
Oxide Semiconductor ◽  
Current Mirror ◽  
Ecg Signals ◽  
Transconductance Amplifier ◽  
And Performance

This paper proposed a design and performance analysis of current mirror operational transconductance amplifier (OTA) in 45 nm and 90 nm complementary metal oxide semiconductor (CMOS) technology for bio-medical application. Both OTAs were designed and simulated using Synopsys tools and the simulation results were analysed thoroughly. The OTAs were designed to be implemented in bio-potential signals detection system where the input signals were amplified and filtered according to the specifications. From the comparative analysis of both OTAs, the 45 nm OTA managed to produce open loop gain of 45 dB, with common mode rejection ratio (CMRR) of 93.2 dB. The 45 nm OTA produced only 1.113 μV√Hz of input referred noise at 1 Hz. The 45 nm OTA also consumed only 28.21 nW of power from ± 0.5 V supply. The low-power consumption aspect displayed by 45 nm OTA made it suitable to be implemented in bio-medical application such as bio-potential signals detection system where it can be used to amplify and filter the electrocardiogram (ECG) signals.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

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