scholarly journals AES-LBBB: AES Mode for Lightweight and BBB-Secure Authenticated Encryption

2021 ◽  
pp. 298-333
Author(s):  
Yusuke Naito ◽  
Yu Sasaki ◽  
Takeshi Sugawara
Keyword(s):  
Integrated Circuit ◽  
Internal State ◽  
Authenticated Encryption ◽  
Backward Compatibility ◽  
Current State ◽  
Security Proof ◽  
Application Specific Integrated Circuit ◽  
Standardization Process ◽  
Beyond Birthday Bound ◽  
State Size

In this paper, a new lightweight authenticated encryption scheme AESLBBB is proposed, which was designed to provide backward compatibility with advanced encryption standard (AES) as well as high security and low memory. The primary design goal, backward compatibility, is motivated by the fact that AES accelerators are now very common for devices in the field; we are interested in designing an efficient and highly secure mode of operation that exploits the best of those AES accelerators. The backward compatibility receives little attention in the NIST lightweight cryptography standardization process, in which only 3 out of 32 round-2 candidates are based on AES. Our mode, LBBB, is inspired by the design of ALE in the sense that the internal state size is a minimum 2n bits when using a block cipher of length n bits for the key and data. Unfortunately, there is no security proof of ALE, and forgery attacks have been found on ALE. In LBBB, we introduce an additional feed from block cipher’s output to the key state via a certain permutation λ, which enables us to prove beyond-birthday-bound (BBB) security. We then specify its AES instance, AES-LBBB, and evaluate its performance for (i) software implementation on a microcontroller with an AES coprocessor and (ii) hardware implementation for an application-specific integrated circuit (ASIC) to show that AES-LBBB performs better than the current state-of-the-art Remus-N2 with AES-128.

scholarly journals SKINNY-AEAD and SKINNY-Hash

2020 ◽  
pp. 88-131 ◽  
Author(s):  
Christof Beierle ◽  
Jérémy Jean ◽  
Stefan Kölbl ◽  
Gregor Leander ◽  
Amir Moradi ◽  
...  
Keyword(s):  
Internal State ◽  
Block Ciphers ◽  
Third Party ◽  
Authenticated Encryption ◽  
Lightweight Cryptography ◽  
The Family ◽  
Encryption Schemes ◽  
Standardization Process

We present the family of authenticated encryption schemes SKINNY-AEAD and the family of hashing schemes SKINNY-Hash. All of the schemes employ a member of the SKINNY family of tweakable block ciphers, which was presented at CRYPTO 2016, as the underlying primitive. In particular, for authenticated encryption, we show how to instantiate members of SKINNY in the Deoxys-I-like ΘCB3 framework to fulfill the submission requirements of the NIST lightweight cryptography standardization process. For hashing, we use SKINNY to build a function with larger internal state and employ it in a sponge construction. To highlight the extensive amount of third-party analysis that SKINNY obtained since its publication, we briefly survey the existing cryptanalysis results for SKINNY-128-256 and SKINNY-128-384 as of February 2020. In the last part of the paper, we provide a variety of ASIC implementations of our schemes and propose new simple SKINNY-AEAD and SKINNY-Hash variants with a reduced number of rounds while maintaining a very comfortable security margin. https://csrc.nist.gov/Projects/Lightweight-Cryptography

scholarly journals From Combined to Hybrid: Making Feedback-based AE even Smaller

2020 ◽  
pp. 417-445
Author(s):  
Avik Chakraborti ◽  
Nilanjan Datta ◽  
Ashwin Jha ◽  
Snehal Mitragotri ◽  
Mridul Nandi
Keyword(s):  
Large Class ◽  
Block Cipher ◽  
Internal State ◽  
Block Size ◽  
The State ◽  
Combined Effect ◽  
Authenticated Encryption ◽  
Feedback Function ◽  
Novel Approach ◽  
State Size

In CHES 2017, Chakraborti et al. proposed COFB, a rate-1 sequential block cipher-based authenticated encryption (AE) with only 1.5n-bit state, where n denotes the block size. They used a novel approach, the so-called combined feedback, where each block cipher input has a combined effect of the previous block cipher output and the current plaintext block. In this paper, we first study the security of a general rate-1 feedback-based AE scheme in terms of its overall internal state size. For a large class of feedback functions, we show that the overlying AE scheme can be attacked in 2r queries if the internal state size is n + r bits for some r ≥ 0. This automatically shows that a birthday bound (i.e. 2n/2 queries) secure AE scheme must have at least 1.5n-bit state, whence COFB is almost-optimal (use 1.5n-bit state and provides security up to 2n/2/n queries). We propose a new feedback function, called the hybrid feedback or HyFB, which is a hybrid composition of plaintext and ciphertext feedbacks. HyFB has a key advantage of lower XOR counts over the combined feedback function. This essentially helps in reducing the hardware footprint. Based on HyFB we propose a new AE scheme, called HyENA, that achieves the state size, rate, and security of COFB. In addition, HyENA has significantly lower XOR counts as compared to COFB, whence it is expected to have a smaller implementation as compared to COFB.

scholarly journals Simultaneous Voltage and Current Measurement Instrumentation Amplifier for ECG and PPG Monitoring

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 679
Author(s):  
Jongpal Kim
Keyword(s):  
Integrated Circuit ◽  
Cardiovascular Health ◽  
Current Noise ◽  
Instrumentation Amplifier ◽  
Current Sensing ◽  
Application Specific Integrated Circuit ◽  
Time Division ◽  
Electrocardiogram Ecg ◽  
First Time ◽  
Application Specific

An instrumentation amplifier (IA) capable of sensing both voltage and current at the same time has been introduced and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) measurements for cardiovascular health monitoring applications. The proposed IA can switch between the voltage and current sensing configurations in a time–division manner faster than the ECG and PPG bandwidths. The application-specific integrated circuit (ASIC) of the proposed circuit design was implemented using 180 nm CMOS fabrication technology. Input-referred voltage noise and current noise were measured as 3.9 µVrms and 172 pArms, respectively, and power consumption was measured as 34.9 µA. In the current sensing configuration, a current noise reduction technique is applied, which was confirmed to be a 25 times improvement over the previous version. Using a single IA, ECG and PPG can be monitored in the form of separated ECG and PPG signals. In addition, for the first time, a merged ECG/PPG signal is acquired, which has features of both ECG and PPG peaks.

CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS

1994 ◽  
Vol 04 (04) ◽  
pp. 501-516 ◽  
Author(s):  
BOGDAN T. FIJALKOWSKI ◽  
JAN W. KROSNICKI
Keyword(s):  
Direct Current ◽  
Integrated Circuit ◽  
Environmentally Friendly ◽  
Alternating Current ◽  
Switching Frequency ◽  
Neuro Fuzzy ◽  
Interior Permanent Magnet ◽  
Application Specific Integrated Circuit ◽  
Computer Processor ◽  
Application Specific

Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.

scholarly journals One-chip analog circuits for a new type of plasma wave receiver on board space missions

2017 ◽  
Vol 6 (1) ◽  
pp. 159-167 ◽  
Author(s):  
Takahiro Zushi ◽  
Hirotsugu Kojima ◽  
Hiroshi Yamakawa
Keyword(s):  
Plasma Wave ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Test System ◽  
Analog To Digital ◽  
Application Specific Integrated Circuit ◽  
New Type ◽  
Narrow Dynamic Range ◽  
Asic Chip

Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm  ×  1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

scholarly journals Permutation-Based Lightweight Authenticated Cipher with Beyond Conventional Security

2021 ◽  
Vol 2021 ◽  
pp. 1-9
Author(s):  
Ping Zhang
Keyword(s):  
Hardware Implementation ◽  
Authenticated Encryption ◽  
Resource Constrained ◽  
Large Capacity ◽  
Efficiency Optimization ◽  
Security Proof ◽  
Almost All ◽  
Resource Constrained Devices ◽  
Constrained Devices

Lightweight authenticated ciphers are specially designed as authenticated encryption (AE) schemes for resource-constrained devices. Permutation-based lightweight authenticated ciphers have gained more attention in recent years. However, almost all of permutation-based lightweight AE schemes only ensure conventional security, i.e., about c / 2 -bit security, where c is the capacity of the permutation. This may be vulnerable for an insufficiently large capacity. This paper focuses on the stronger security guarantee and the better efficiency optimization of permutation-based lightweight AE schemes. On the basis of APE series (APE, APE R I , APE O W , and APE C A ), we propose a new improved permutation-based lightweight online AE mode APE + which supports beyond conventional security and concurrent absorption. Then, we derive a simple security proof and prove that APE + enjoys at most about min r , c -bit security, where r is the rate of the permutation. Finally, we discuss the properties of APE + on the hardware implementation.

The diffraction detector for the EMD of the CSNS

2021 ◽  
Vol 16 (12) ◽  
pp. P12018
Author(s):  
Q. Yu ◽  
B. Tang ◽  
C. Huang ◽  
Y. Wei ◽  
S. Chen ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Detection Efficiency ◽  
Grazing Angle ◽  
Incident Neutron ◽  
Silicon Photomultiplier ◽  
Detector Module ◽  
Neutron Wavelength ◽  
Thermal Neutron Detector ◽  
Application Specific Integrated Circuit ◽  
Design And Manufacture

Abstract On 23rd August 2018, the China Spallation Neutron Source (CSNS) located in Dongguan operated 4 neutron instruments. In the future, twenty neutron spectrometers will be built to provide multidisciplinary platforms for scientific research by national institutions, universities, and industries. Engineering Material Diffractometer (EMD), which will be used for strain measurements in engineering materials and components, will be constructed at the Beamline 8 in 2022. A novel thermal neutron detector, which will comply with the requirements of EMD application, is being developed. This detector will consist of 6LiF/ZnS(Ag) scintillation screens, wavelength shifting fiber (WLSF) arrays, a silicon photomultiplier (SiPM) and Application Specific Integrated Circuit (ASIC) read-out electronics. Each scintillation screen will be inclined with respect to the incident neutron beam at a grazing angle θ = 17°. Such geometry will not only improve the spatial resolution of detectors but also the neutron detection efficiency. The prototype of detector module has been tested at the neutron Beamline 20 at the CSNS. The experimental results obtained for this prototype illustrate that the pixel size of detector module is 3 mm and the detection efficiency exceeds 40% at the neutron wavelength of 1 Å. Based on these results, we design and manufacture the final version of the detector for the EMD application, which is characterized by low power consumption, highly integrated and easy to install. 70 such detectors will be installed till the end of 2021.

scholarly journals Recent Advances in ASIC Development for Enhanced Performance M-Sequence UWB Systems

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4812 ◽  
Author(s):  
Pavol Galajda ◽  
Martin Pecovsky ◽  
Miroslav Sokol ◽  
Martin Kmec ◽  
Dusan Kocur
Keyword(s):  
Integrated Circuit ◽  
Short Range ◽  
Functional System ◽  
Ultra Wideband ◽  
Radar Sensors ◽  
Sensing Applications ◽  
Radio Detection ◽  
M Sequence ◽  
Application Specific Integrated Circuit ◽  
On Chip

Short-range ultra-wideband (UWB) radar sensors belong to very promising sensing techniques that have received vast attention recently. The M-sequence UWB sensing techniques for radio detection and ranging feature several advantages over the other short-range radars, inter alia superior integration capabilities. The prerequisite to investigate their capabilities in real scenarios is the existence of physically available hardware, i.e., particular functional system blocks. In this paper, we present three novel blocks of M-sequence UWB radars exploiting application-specific integrated circuit (ASIC) technology. These are the integrated 15th-order M-sequence radar transceiver on one chip, experimental active Electronic Communication Committee (ECC) bandpass filter, and miniature transmitting UWB antenna with an integrated amplifier. All these are custom designs intended for the enhancement of capabilities of an M-sequence-based system family for new UWB short-range sensing applications. The design approaches and verification of the manufactured prototypes by measurements of the realized circuits are presented in this paper. The fine balance on technology capabilities (Fc of roughly 120 GHz) and thoughtful design process of the proposed blocks is the first step toward remarkably minimized devices, e.g., as System on Chip designs, which apparently allow broadening the range of new applications.

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

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