Design of System Level Architecture of Multi-Core with Array Mapping Based on Floating Processing Factor-Fast Fourier Transform for Health Informatics Application

2021 ◽  
Vol 11 (10) ◽  
pp. 2639-2645
Author(s):  
T. Sivaprakasam ◽  
M. Ramasamy
Keyword(s):  
Health Informatics ◽  
High Speed ◽  
System Level ◽  
Processing Factor ◽  
Fft Processor ◽  
Operating Rate ◽  
On Chip ◽  
Access Patterns ◽  
Fft Algorithms ◽  
Autonomous Detection

In FFT algorithms memory access patterns prevent multiple architectures from achieving high machine use, particularly when parallel processing is needed to achieve the desired efficiency rates. Beginning with the extremely powerful FFT heart, the on-chip memory hierarchy for the multicored FFT processor, is co-designed and linked on-chip. We have shown that the Floating Processing Factor (FPPE) proposed achieves greater operating rate and lower power for the application of health informatics. This test mechanism aids in omission of faulty cores and autonomous detection also makes elegant multi-core architecture degradation feasible. Experimental results illustrate that the anticipated design is scalable widely in terms of performance overhead and hardware overhead which makes it appropriate to many-cores with more than a thousand processing cores through Low Power and High Speed.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

High-Speed On-Chip Event Counters for Embedded Systems

2009 ◽  
Author(s):  
Nilanjan Mukherjee ◽  
Artur Pogiel ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  
Embedded Systems ◽  
High Speed ◽  
On Chip

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

Removal Mechanism of Titanium Alloy Ti6Al4V Based on Single-Grain High Speed Grinding Test

2011 ◽  
Vol 487 ◽  
pp. 39-43 ◽  
Author(s):  
L. Tian ◽  
Yu Can Fu ◽  
W.F. Ding ◽  
Jiu Hua Xu ◽  
H.H. Su
Keyword(s):  
Titanium Alloy ◽  
High Speed ◽  
Chip Thickness ◽  
Wheel Speed ◽  
High Speed Grinding ◽  
Tc4 Alloy ◽  
Grinding Mechanism ◽  
Single Grain ◽  
On Chip ◽  
Titanium Alloy Ti6al4v

Single-grain grinding test plays an important part in studying the high speed grinding mechanism of materials. In this paper, a new method and experiment system for high speed grinding test with single CBN grain are presented. In order to study the high speed grinding mechanism of TC4 alloy, the chips and grooves were obtained under different wheel speed and corresponding maximum undeformed chip thickness. Results showed that the effects of wheel speed and chip thickness on chip formation become obvious. The chips were characterized by crack and segment band feature like the cutting segmented chips of titanium alloy Ti6Al4V.

PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS

2009 ◽  
Vol 18 (02) ◽  
pp. 255-269 ◽  
Author(s):  
JUN HO BAHN ◽  
JUNG SOOK YANG ◽  
WEN-HSIANG HU ◽  
NADER BAGHERZADEH
Keyword(s):  
Data Communication ◽  
Digital Signal ◽  
Variable Number ◽  
Data Locality ◽  
Communication Traffic ◽  
On Chip ◽  
Fft Algorithms ◽  
Signal Processors ◽  
Parallel Fft ◽  
Parallel Fft Algorithm

This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

scholarly journals Thermographic Study of Chip Temperature in High-Speed Dry Milling Magnesium Alloys

2016 ◽  
Vol 7 (2) ◽  
pp. 86-92 ◽  
Author(s):  
Józef Kuczmaszewski ◽  
Ireneusz Zagórski ◽  
Piotr Zgórniak
Keyword(s):  
Temperature Measurement ◽  
Magnesium Alloys ◽  
High Speed ◽  
Machining Process ◽  
Dry Milling ◽  
Technological Parameters ◽  
Chip Temperature ◽  
Thermographic Study ◽  
On Chip ◽  
The Impact

Abstract This paper presents an overview of the state of knowledge on temperature measurement in the cutting area during magnesium alloy milling. Additionally, results of own research on chip temperature measurement during dry milling of magnesium alloys are included. Tested magnesium alloys are frequently used for manufacturing elements applied in the aerospace industry. The impact of technological parameters on the maximum chip temperature during milling is also analysed. This study is relevant due to the risk of chip ignition during the machining process.

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