scholarly journals Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

2021 ◽  
Vol 11 (24) ◽  
pp. 12151
Author(s):  
Tae Jun Ahn ◽  
Sung Kyu Lim ◽  
Yun Seop Yu
Keyword(s):  
Circuit Simulation ◽  
Three Dimensional ◽  
Propagation Delay ◽  
Model Parameters ◽  
Interface Trap ◽  
Flip Flop ◽  
Trap Charge ◽  
Noise Margin ◽  
Simulation Results ◽  
Trap Charges

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

2021 ◽  
Vol 21 (8) ◽  
pp. 4252-4257
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Interface Trap ◽  
Charge Effects ◽  
Trap Charge ◽  
Interlayer Dielectric ◽  
Threshold Voltages ◽  
Propagation Delays ◽  
Aided Design

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

2020 ◽  
pp. 2150051
Author(s):  
Shivangi Chandrakar ◽  
Deepika Gupta ◽  
Manoj Kumar Majumder
Keyword(s):  
Power Dissipation ◽  
Three Dimensional ◽  
Propagation Delay ◽  
Model Parameters ◽  
3D Integration ◽  
Coupling Behavior ◽  
Power Delay Product ◽  
Silicon Vias ◽  
The Impact

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

scholarly journals Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 887
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Circuit Simulation ◽  
Electrical Coupling ◽  
Ring Oscillator ◽  
Model Parameters ◽  
Flip Flop ◽  
Circuit Simulator ◽  
Aided Design ◽  
Better Than

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

scholarly journals ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Avireni Srinivasulu ◽  
Madugula Rajesh
Keyword(s):  
Low Power ◽  
Propagation Delay ◽  
Vlsi Implementation ◽  
Model Parameters ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Pass Transistor ◽  
Simulation Results ◽  
Parasitic Effects ◽  
Power Diode

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

scholarly journals 3D Interactive Visualization Method of Urban Waterlogging Based on Cesium

2019 ◽  
Vol 1 ◽  
pp. 1-1
Author(s):  
Xu Zhang ◽  
Wei Zhou ◽  
Jie Shen ◽  
Lukáš Herman ◽  
Yixian Du
Keyword(s):  
3D Visualization ◽  
Three Dimensional ◽  
Interactive Visualization ◽  
Model Parameters ◽  
Visualization Method ◽  
Process Data ◽  
Visualization System ◽  
Simulation Based ◽  
Simulation Results ◽  
3D Scene

<p><strong>Abstract.</strong> Urban waterlogging, as a common natural disaster in China, seriously restricted the development of society. Nowadays, while the computer technology is developing continuously, the urban waterlogging model is also constantly improved. These models can simulate the process of urban waterlogging, but the simulation results are not intuitive. So it is difficult for users to understand how the model works. Therefore, it is important to find a way to show the simulation results so that people can see the waterlogging simulation intuitively. Cesium, as a three-dimensional visualization platform, can reproduce the process of the urban waterlogging. It will make sense if we could show the simulation results on the Cesium platform. Nowadays, many studies focus on both urban waterlogging and visualization methods. However, there are fewer studies on the combination of the two, especially the interactive visualization of urban waterlogging under parameter adjustment. Therefore, this paper mainly focuses on urban three-dimensional interactive visualization method based on Cesium.</p><p>On the one hand, the three-dimensional visualization of the urban waterlogging simulation facilitates the intuitive expression of the simulation results. Without visualization, the results of the simulation are only some complicated and unintuitive figures for most non-experts. On the other hand, visualization based on the Cesium platform can better adapt to the cross-platform application. It can better meet the needs of different terminal devices of different users for the visualization platform, so that users can obtain the disaster information more accurately, consistently and intuitively. It is conducive for management departments to respond to sudden disasters more quickly and efficiently.</p><p>This research aims to propose a three-dimensional dynamic interactive visualization method for urban waterlogging. Particularly, we hope to find out how to integrate urban waterlogging model and 3D visualization platform. With this 3D visualization platform, we can combine the advantages of the SWMM (Storm Water Management Model) and Cesium platform. Using this platform, it will be easier and more effective to respond to disasters for the masses and management departments.</p><p>The following two issues are resolved in this study: i) How do model parameters affect the urban waterlogging simulation and visualization results? ii) How to integrate SWMM and Cesium 3D visualization platform?</p><p>In order to address the above research objectives, we will apply the following methodologies: i) We will analyse the parameters of the SWMM for the urban waterlogging visualization. Under the premise of understanding the development process of the urban waterlogging, we will analyse the modelling principle of the urban waterlogging, the mechanism of each part of the model separately. Then, we will find out the method of determining the model parameters of urban waterlogging and its influence on the simulation visualization results. ii) We will study integration methods of urban waterlogging model and 3D visualization platform. We will analyse the mechanism and process of urban waterlogging. We will also calculate the urban waterlogging process data by the SWMM, and establish a three-dimensional visualization platform by the node.js and Cesium, which can dynamically show the process of urban waterlogging. iii) We will complete the design and implementation of the interactive visualization platform of urban waterlogging. According to the above research, taking the Xianlin Campus of Nanjing Normal University as an example, we will build a dynamic interactive visualization system of urban waterlogging simulation based on Cesium. We will also verify the effectiveness of the system by comparing it with actual flood situation.</p><p>With this study, we expect to answer how model parameters affect the urban waterlogging simulation and visualization results. As expected results, we plan to build an interactive visualization system of urban waterlogging simulation based on Cesium, publish the flood calculation results into the 3D scene. This will make urban waterlogging process shown in the 3D scene. This visualization system is designed for different users, including specialists, government and individual. It means that you can use the system easily even if you are non-cartographers or non-IT-specialists.</p>

scholarly journals Design and Analysis of Gate All Around Tunnel FET based SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1492-1500
Keyword(s):  
Circuit Simulation ◽  
Research Work ◽  
Device Simulation ◽  
Leakage Power ◽  
Subthreshold Slope ◽  
Noise Margin ◽  
Tunnel Fet ◽  
Sram Cell ◽  
Simulation Results ◽  
Strong Control

Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The main objective of this research work is to explore the prospects of using GAATFET device topology for designing low power and reliable SRAM cell. In this work both n-type and p-type Tunnel FET devices have been designed and simulated using Cogenda Visual TCAD tool. Verilog-A model relying on look up tables that are extracted through device simulations has been designed for performing circuit simulations of 6T and 8T SRAM cell involving these novel devices. Device simulation results show that both NTFET and PTFET devices exhibits excellent ION/IOFF ratio and steep subthreshold slope. NTFET device simulation results show 21.2 mV/decade of subthreshold slope and ION/IOFF ratio of 1013. PTFET device has ON current of the similar order as that of NTFET and has extremely low value of OFF current of less than 1 pA. Circuit simulation results show that by using optimized sizing of transistors in outward NTFET access transistor based 6T SRAM cell leads to reliable and fast read and write operation with acceptable values of noise margin. 6T TFET based SRAM cell achieves leakage power reduction by 77.5% in comparison to leakage power consumed by 8T TFET based SRAM thereby making it a favorable choice for memory design.

scholarly journals Modeling of German Low Voltage Cables with Ground Return Path

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1265 ◽  
Author(s):  
Johanna Geis-Schroer ◽  
Sebastian Hubschneider ◽  
Lukas Held ◽  
Frederik Gielnik ◽  
Michael Armbruster ◽  
...  
Keyword(s):  
Low Voltage ◽  
Measurement Data ◽  
Analytical Calculation ◽  
Laboratory Measurement ◽  
Model Parameters ◽  
Calculation Methods ◽  
Modeling Approach ◽  
Measurement Results ◽  
Simulation Results ◽  
Return Path

In this contribution, measurement data of phase, neutral, and ground currents from real low voltage (LV) feeders in Germany is presented and analyzed. The data obtained is used to review and evaluate common modeling approaches for LV systems. An alternative modeling approach for detailed cable and ground modeling, which allows for the consideration of typical German LV earthing conditions and asymmetrical cable design, is proposed. Further, analytical calculation methods for model parameters are described and compared to laboratory measurement results of real LV cables. The models are then evaluated in terms of parameter sensitivity and parameter relevance, focusing on the influence of conventionally performed simplifications, such as neglecting house junction cables, shunt admittances, or temperature dependencies. By comparing measurement data from a real LV feeder to simulation results, the proposed modeling approach is validated.

Design of finite-time guidance law based on observer and head-pursuit theory

2021 ◽  
pp. 095441002098456
Author(s):  
Chenqi Zhu
Keyword(s):  
Finite Time ◽  
Three Dimensional ◽  
Hypersonic Vehicle ◽  
Two Dimensional ◽  
Dimensional Model ◽  
Reaching Law ◽  
Guidance Law ◽  
Fast Power ◽  
Simulation Results ◽  
Guidance Laws

In order to improve the guiding accuracy in intercepting the hypersonic vehicle, this article presents a finite-time guidance law based on the observer and head-pursuit theory. First, based on a two-dimensional model between the interceptor and target, this study applies the fast power reaching law to head-pursuit guidance law so that it can alleviate the chattering phenomenon and ensure the convergence speed. Second, target maneuvers are considered as system disturbances, and the head-pursuit guidance law based on an observer is proposed. Furthermore, this method is extended to a three-dimensional case. Finally, comparative simulation results further verify the superiority of the guidance laws designed in this article.

scholarly journals A flexible framework for sequential estimation of model parameters in computational hemodynamics

2020 ◽  
Vol 7 (1) ◽  
Author(s):  
Christopher J. Arthurs ◽  
Nan Xiao ◽  
Philippe Moireau ◽  
Tobias Schaeffter ◽  
C. Alberto Figueroa
Keyword(s):  
Unscented Kalman Filter ◽  
Three Dimensional ◽  
Synthetic Data ◽  
Sequential Estimation ◽  
Wall Material ◽  
Patient Specific ◽  
Model Parameters ◽  
Computational Framework ◽  
Lumped Parameter ◽  
Estimation Of Model Parameters

AbstractA major challenge in constructing three dimensional patient specific hemodynamic models is the calibration of model parameters to match patient data on flow, pressure, wall motion, etc. acquired in the clinic. Current workflows are manual and time-consuming. This work presents a flexible computational framework for model parameter estimation in cardiovascular flows that relies on the following fundamental contributions. (i) A Reduced-Order Unscented Kalman Filter (ROUKF) model for data assimilation for wall material and simple lumped parameter network (LPN) boundary condition model parameters. (ii) A constrained least squares augmentation (ROUKF-CLS) for more complex LPNs. (iii) A “Netlist” implementation, supporting easy filtering of parameters in such complex LPNs. The ROUKF algorithm is demonstrated using non-invasive patient-specific data on anatomy, flow and pressure from a healthy volunteer. The ROUKF-CLS algorithm is demonstrated using synthetic data on a coronary LPN. The methods described in this paper have been implemented as part of the CRIMSON hemodynamics software package.

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