scholarly journals Gate-All-Around FETs: Nanowire and Nanosheet Structure

2020 ◽  
Author(s):  
Jun-Sik Yoon ◽  
Jinsu Jeong ◽  
Seunghwan Lee ◽  
Junjong Lee ◽  
Rock-Hyun Baek
Keyword(s):  
Low Power ◽  
High Performance ◽  
The Other ◽  
Short Channel ◽  
Technology Node ◽  
Channel Characteristics ◽  
Other Hand ◽  
Rc Delay

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

Compact Hardware Implementations of MISTY1 Block Cipher

2017 ◽  
Vol 27 (03) ◽  
pp. 1850037 ◽  
Author(s):  
Yasir ◽  
Ning Wu ◽  
Xiaoqiang Zhang
Keyword(s):  
Low Power ◽  
Block Cipher ◽  
Comprehensive Analysis ◽  
The Other ◽  
Key Generation ◽  
Round Function ◽  
Other Hand ◽  
Hardware Implementations ◽  
Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

scholarly journals Low Power based Dynamic TSPC D flip flop for High Performance Applications

2020 ◽  
Vol 9 (8) ◽  
pp. 758-762
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Memory Cell ◽  
Research Center ◽  
Short Channel ◽  
Flip Flop ◽  
Force Application ◽  
Effect Transistor

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

Cost-Effective and Highly Reliable 6F2 Multi-Gigabit DRAM in 60nm Technology Node for Low Power and High Performance Applications

2006 ◽  
Author(s):  
D. Ha ◽  
J. H. Kim ◽  
T. H. An ◽  
S. S. Lee ◽  
S. H. Jang ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Cost Effective ◽  
Technology Node

Flexible PLED displays and related technologies

2004 ◽  
Vol 814 ◽  
Author(s):  
G. Nisato ◽  
C. Mutsaers ◽  
H. Buijk ◽  
P. Duineveld ◽  
E. Janssen ◽  
...  
Keyword(s):  
High Performance ◽  
Structural Integrity ◽  
Low Voltage ◽  
Flexible Substrate ◽  
Fast Response ◽  
Industrial Applications ◽  
Hole Transport ◽  
The Other ◽  
Enabling Technology ◽  
Other Hand

AbstractFlexible, free shape displays are the enabling technology for new robust, lightweight, extremely thin, portable electronic devices. Polymer Light Emitting Diodes (PLED) are especially suited for these applications, due to their fast response time, low voltage, high luminous efficiency and viewing angle performance. On the other hand, PLED displays are extremely sensitive to moisture and oxygen. Substrate materials provided with high performance hermetic and conducting layers are therefore an essential component for manufacturing these flexible devices. Polymer based substrates provide the necessary mechanical flexibility; they also require several thin, brittle, functional inorganic layers such diffusion barriers and transparent electrodes. The structural integrity, dimensional stability and thermal properties of the substrate stack are crucial to insure device functionality and reliability. For polymer-based substrate several effects lead to dimensional variation of the substrates, such as solvent uptake, physical ageing of the polymer base, thermal expansion and stress induced deformations. These effects must be taken into account to successfully perform classic photolithographic steps.Ink-jet printing is a critical enabling technology for flexible PLED displays, providing a customizable means to dispense solution-based polymers onto a flexible substrate, allowing for multi-color devices. On the other hand, IJP must meet several challenges, especially to comply with industrial applications. For example, accurate landing position of the droplets to form homogeneous hole-transport and electroluminescent layers as well as good wetting characteristic of the substrates must be obtained with reliable high throughput techniques.

High Performance Fabrics in Body Protective Systems

2016 ◽  
Vol 880 ◽  
pp. 132-135 ◽  
Author(s):  
Selim Gürgen ◽  
Melih Cemal Kuşhan
Keyword(s):  
Kinetic Energy ◽  
High Performance ◽  
The Other ◽  
Body Armor ◽  
Personal Protection ◽  
Military Vehicles ◽  
Living Space ◽  
Other Hand ◽  
Lightweight Structure ◽  
Protective Systems

High performance fabrics are preferable for armor systems due to their lightweight structure and flexibility. High performance fabrics are generally used in body armor design for personal protection. However, these fabrics are utilized to cover the living space in military vehicles such as helicopters and armored vehicles. Besides, pilot seats in combat helicopters are included in utilization area of high performance fabrics. On the other hand armor is defined as a defensive covering to protect body or something against attacking threats. Protection is provided by absorbing the kinetic energy of the attacking threats and stopping them before any damage occurs in the target. This paper offers an overview of high performance fabrics in armor systems.

scholarly journals Authentication of Straight Whiskey by Determination of the Ratio of Furfural to 5-Hydroxymethyl-2-Furaldehyde

1999 ◽  
Vol 82 (4) ◽  
pp. 997-1001 ◽  
Author(s):  
James Jaganathan ◽  
Sumer M Dugar
Keyword(s):  
High Performance ◽  
Chromatographic Method ◽  
High Performance Liquid Chromatographic ◽  
The Other ◽  
Color Intensity ◽  
Other Hand ◽  
Liquid Chromatographic Method ◽  
Oak Barrels ◽  
Liquid Chromatographic

Abstract Bureau of Alcohol, Tobacco and Firearms regulations require that a straight whiskey be aged in a freshly charred oak barrel for a minimum of 2 years and that it not be colored with added caramel. The regulations, however, permit addition of caramel in blended whiskeys. Blended whiskeys are usually produced by mixing a straight whiskey with neutral spirits which causes loss of color intensity. Caramel addition is permitted to compensate for this loss. Thus, it is not possible to authenticate the standard of identity of a straight whiskey by measurement of color intensity. Our investigations suggest that furfural (2-furaldehyde) and 5-hydroxymethyl-2-furaldehyde are imparted into a straight whiskey during aging in a freshly charred oak barrel. Caramel, on the other hand, imparts only 5-hydroxymethyl-2-furaldehyde. Thus, the measurement of the concentrations of furfural and 5-hydroxymethyl-2-furaldehyde and their ratio could effectively authenticate the standard of identity of straight whiskeys. This study shows that straight whiskeys aged in freshly charred oak barrels for a period of 2 years or more have a 2:1 or higher ratio of furfural to 5-hydroxymethyl-2-furaldehyde. A high-performance liquid chromatographic method for the determination of furfural and 5-hyroxy- methyl-2-furaldehyde at low parts-per-million levels is described.

scholarly journals A Comprehensive Approach to Monitoring Pipeline River and Stream Crossings

2000 ◽  
Author(s):  
Michelle L. Sorensen ◽  
Craig D. Malcovish
Keyword(s):  
Comprehensive Approach ◽  
The Other ◽  
Aerial Photographs ◽  
River Engineering ◽  
Stream Channel ◽  
Channel Stability ◽  
Regulatory Requirements ◽  
Pipeline Construction ◽  
Channel Characteristics ◽  
Other Hand

There are strict regulatory requirements for pipeline construction at river and stream crossings. The requirements for monitoring, surveillance and maintenance of existing crossings on the other hand are limited to a few lines in Section 10 of CSA Z662-99. Systematic procedures for assessing stream channel stability are not readily available to the operators of pipelines. As a consequence, many monitoring and inspection programs focus more on detecting exposures than on preventing them. In this paper, the AEC Pipelines Ltd. approach to monitoring river and stream crossings is reviewed and discussed. The program involves application of basic geomorphic concepts and use of aerial photographs to define channel characteristics at crossing sites and to determine which crossings may be subject to future channel instability or erosion problems. From these in-house evaluations, decisions are made to either proceed with more in-depth assessments by river engineering specialists or continue with routine aerial and ground surveillance. As part of the overall program, procedures for completing routine channel surveys and a checklist of data to be gathered during regular reconnaissance trips have been developed.

scholarly journals A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud

2022 ◽  
Vol 15 (3) ◽  
pp. 1-31
Author(s):  
Shulin Zeng ◽  
Guohao Dai ◽  
Hanbo Sun ◽  
Jun Liu ◽  
Shiyao Li ◽  
...  
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
High Performance ◽  
Deep Neural Networks ◽  
Cost Effective ◽  
General Purpose ◽  
The Other ◽  
Private Cloud ◽  
Single Task ◽  
Other Hand

INFerence-as-a-Service (INFaaS) has become a primary workload in the cloud. However, existing FPGA-based Deep Neural Network (DNN) accelerators are mainly optimized for the fastest speed of a single task, while the multi-tenancy of INFaaS has not been explored yet. As the demand for INFaaS keeps growing, simply increasing the number of FPGA-based DNN accelerators is not cost-effective, while merely sharing these single-task optimized DNN accelerators in a time-division multiplexing way could lead to poor isolation and high-performance loss for INFaaS. On the other hand, current cloud-based DNN accelerators have excessive compilation overhead, especially when scaling out to multi-FPGA systems for multi-tenant sharing, leading to unacceptable compilation costs for both offline deployment and online reconfiguration. Therefore, it is far from providing efficient and flexible FPGA virtualization for public and private cloud scenarios. Aiming to solve these problems, we propose a unified virtualization framework for general-purpose deep neural networks in the cloud, enabling multi-tenant sharing for both the Convolution Neural Network (CNN), and the Recurrent Neural Network (RNN) accelerators on a single FPGA. The isolation is enabled by introducing a two-level instruction dispatch module and a multi-core based hardware resources pool. Such designs provide isolated and runtime-programmable hardware resources, which further leads to performance isolation for multi-tenant sharing. On the other hand, to overcome the heavy re-compilation overheads, a tiling-based instruction frame package design and a two-stage static-dynamic compilation, are proposed. Only the lightweight runtime information is re-compiled with ∼1 ms overhead, thus guaranteeing the private cloud’s performance. Finally, the extensive experimental results show that the proposed virtualized solutions achieve up to 3.12× and 6.18× higher throughput in the private cloud compared with the static CNN and RNN baseline designs, respectively.

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