One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable.
Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders.
All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology.
This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability.
This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints.
The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference.
A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.
Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method
