Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes

2021 ◽  
Author(s):  
Gurleen Dhillon ◽  
Karmjit Singh Sandha
Keyword(s):  
Carbon Nanotube ◽  
Integrated Circuit ◽  
Promising Result ◽  
Propagation Delay ◽  
Multi Walled Carbon Nanotube ◽  
The Stability ◽  
Power Delay Product ◽  
Dissipation Power ◽  
Technology Nodes ◽  
Transmission Line Models

The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

Design of ternary subtractor using multiplexers

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tulasi Naga Jyothi Kolanti ◽  
Vasundhara Patel K.S.
Keyword(s):  
Field Effect Transistors ◽  
Process Variations ◽  
Propagation Delay ◽  
Channel Length ◽  
Binary Decision ◽  
Content Type ◽  
The Stability ◽  
Power Delay Product ◽  
Ternary Decision Diagram ◽  
Logic Functions

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

CNT as Interconnects

2020 ◽  
pp. 130-159
Author(s):  
Karmjit Singh Sandha
Keyword(s):  
Comparative Analysis ◽  
Equivalent Circuit ◽  
Integrated Circuit ◽  
Equivalent Circuit Model ◽  
Global Level ◽  
Electrical Equivalent Circuit ◽  
Swcnt Bundle ◽  
Impedance Parameters ◽  
Power Delay Product ◽  
Technology Nodes

The chapter will start with brief introduction to the interconnects and its importance in an integrated circuit at deep sub-micron technology nodes. The brief discussion about the concept of scaling, interconnects models, and material in use are presented. The limitations of conventional materials at scaled down technology nodes will be discussed next. The focus of the chapter is to present the electrical equivalent circuit model to estimate the impedance parameters of SWCNT bundle and MWCNT bundle as interconnects at different nano-scaled technology nodes for global level interconnect length. Using ESC model of SWCNT, MWCNT, and copper, the performance comparative analysis for delay and power delay product (PDP) will be presented for different interconnect lengths at nano-scaled technology nodes. Finally, the chapter summary and conclusion will be written at the end of the chapter.

Comparative study of the stability of sulfide materials encapsulated in and expelled from multi-walled carbon nanotube capsules

Carbon ◽  
2011 ◽  
Vol 49 (1) ◽  
pp. 342-346 ◽  
Author(s):  
Pedro M.F.J. Costa ◽  
Ujjal K. Gautam ◽  
Yoshio Bando ◽  
Dmitri Golberg
Keyword(s):  
Carbon Nanotube ◽  
Comparative Study ◽  
Multi Walled Carbon Nanotube ◽  
The Stability

Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects

2020 ◽  
Vol 29 (12) ◽  
pp. 2050185 ◽  
Author(s):  
Himanshu Sharma ◽  
Karmjit Singh Sandha
Keyword(s):  
Integrated Circuit ◽  
Fermi Energy ◽  
Large Scale ◽  
Graphene Nanoribbons ◽  
Layer Graphene ◽  
Parasitic Parameters ◽  
On Chip ◽  
Power Delay Product ◽  
Technology Nodes ◽  
The Impact

Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.

scholarly journals Impact of Process Variations on Delay in Carbon Nanotube Based Bus Interconnects At Different Technology Nodes

2019 ◽  
Vol 9 (1) ◽  
pp. 5506-5512
Keyword(s):  
Carbon Nanotube ◽  
Process Variations ◽  
Delay Analysis ◽  
Empirical Formulas ◽  
Single Walled Carbon Nanotube ◽  
Temperature Variations ◽  
Multi Walled Carbon Nanotube ◽  
Technology Nodes ◽  
The Impact ◽  
Nanotube Bundle

This paper presents the impact of process variations in carbon nanotube based advanced bus interconnects such as single walled carbon nanotube (SWCNT), multi walled carbon nanotube (MWCNT) and mixed carbon nanotube bundle (MCB). The impact of temperature variations on paracitics of interconnects for variable interconnects at different technology nodes is analyzed. From the analysis, it reveal that the mixed bundle carbon nanotube offering the lower paracitics even higher temperatures compared to SWCNT and MWCNT which leads to lower delay and crosstalk effect when it is used in bus interconnects. Further we have also done delay analysis by changing the bundle area, number of shells and metallic ratio of three interconnect structures with the insertion of obtained parasitics using empirical formulas. It is proven that the mixed CNT (MCB) interconnect structures offered a lesser delay compared to other CNT interconnect structures. All the analysis has been done using MATLAB at 22nm and 32nm technology nodes.

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