10-Bit, 1GS/S Time-Interleaved SAR ADC

This paper describes the implementation of a 4-channel, 10-bit, 1 GS/s time-interleaved analog to digital converter (TI-ADC) in 65nm CMOS technology. Each channel consists of interleaved T/H and ADC array operating at 250 MS/s, with each ADC array containing 14 timeinterleaved sub-ADCs. This configuration provides high sampling rate even though each subADC works at a moderate sampling rate. We have selected 10-bit successive approximation ADC (SAR ADC) as a sub-ADC, since this architecture is most suitable for low power and medium resolution. SAR ADC works on binary search algorithm, since it resolves 1-bit at a time. The target sampling rate was 20 MS/s in this design, however the sampling rate achieved is 15 MS/s. As a result, the 10-bit SAR ADC operates at 15 MS/s with power consumption of 560 μW at 1.2 V supply and achieves SNDR of 57 dB (i.e. ENOB 9.2 bits) near nyquist rate input. The resulting Figure of Merit (FoM) is 63.5 fJ/step. The achieved DNL and INL is +0.85\-0.9 LSB and +1\-1.1 LSB respectively. The 10-bit SAR ADC occupies an active area of 300 μm × 440 μm. The functionality of single channel TI-SAR ADC has been verified by simulation with input signal frequency of 33.2 MHz and clock frequency of 250 MHz. The desired SNDR of 59.3 dB has been achieved with power consumption of 11.6 mW. This results in a FoM value of 60 fJ/step.

A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications

10.1142/s0218126618502304 ◽

2018 ◽

Vol 27 (14) ◽

pp. 1850230 ◽

Cited By ~ 1

Author(s):

Samaneh Babayan-Mashhadi ◽

Mona Jahangiri-Khah

Keyword(s):

Power Consumption ◽

Supply Voltage ◽

Sampling Rate ◽

Power Saving ◽

Cmos Technology ◽

Sar Adc ◽

Signal Acquisition ◽

Quantization Scheme ◽

Power Efficient ◽

Sensing Applications

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

A 6.4-GS/s 10-b Time-Interleaved SAR ADC with Time-Skew Immune Sampling Network in 28-nm CMOS

10.1142/s0218126620502643 ◽

2020 ◽

Vol 29 (16) ◽

pp. 2050264

Author(s):

Ning Ding ◽

Yusong Mu ◽

Yuping Guo ◽

Teng Chen ◽

Yuchun Chang

Keyword(s):

Power Consumption ◽

Single Channel ◽

Sar Adc ◽

Current Feedback ◽

Sampling Network ◽

Capacitor Mismatch ◽

Multi Phase ◽

Time Interleaved ◽

And Behavior ◽

Design Simplicity

This paper presents a 6.4-GS/s 16-way 10-bit time-interleaved (TI) SAR ADC for wideband wireless applications. A two-stage master–slave hierarchical sampling network, which is immune to the time skew of multi-phase clocks, is introduced to avoid the time-skew calibration for design simplicity and hardware efficiency. To perform low distortion and fast sampling at acceptable power consumption, a linearity- and energy efficiency-improved track-and-hold (T&H) buffer with current-feedback compensation scheme is proposed. Accompanied by its low-output-impedance feature, the buffer obtains adequate bandwidth which can cover the entire ADC Nyquist sampling range. Moreover, the split capacitor DAC combined with a novel nonbinary algorithm is adopted in single-channel ADC, enabling a shorter DAC settling time as well as less switching energy. Capacitor mismatch effect with related design trade-off is discussed and behavior models are built to evaluate the effect of capacitor mismatch on ENOB. An asynchronous self-triggered SAR logic is designed and optimized to minimize the delay on logic paths to match up the acceleration on DAC and comparator. With these proposed techniques, the 10-b sub-ADC achieves a 400-MHz conversion rate with only 3.5-mW power consumption. The circuit is designed and simulated in TSMC 28 HPC process and the results show that the overall ADC achieves 54.6-dB SNDR and 58.1-dB SFDR at Nyquist input while consuming 127-mW power from 1-V/1.5-V supply and achieving a Walden FoM of 45[Formula: see text]fJ/conv-step.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Journal of Electrical Engineering ◽

10.1515/jee-2017-0076 ◽

2017 ◽

Vol 68 (6) ◽

pp. 415-424

Author(s):

Oktay Aytar ◽

Ali Tangel ◽

Engin Afacan

Keyword(s):

Power Consumption ◽

Power Efficiency ◽

Sampling Rate ◽

Control Process ◽

Logic Gates ◽

Cmos Technology ◽

Timing Control ◽

Aspect Ratios ◽

Interleaved Adc ◽

Abstract This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

10.1142/s0218126615500930 ◽

2015 ◽

Vol 24 (06) ◽

pp. 1550093 ◽

Cited By ~ 5

Author(s):

Dengquan Li ◽

Liang Zhang ◽

Zhangming Zhu ◽

Yintang Yang

Keyword(s):

Single Channel ◽

Mode Selection ◽

Sampling Rate ◽

Cmos Technology ◽

Analog To Digital ◽

Timing Errors ◽

Delay Locked Loop ◽

Simulation Results ◽

On Chip ◽

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

Static Switching Dynamic Buffer Circuit

Journal of Engineering ◽

10.1155/2013/646214 ◽

2013 ◽

Vol 2013 ◽

pp. 1-11

Author(s):

A. K. Pandey ◽

R. A. Mishra ◽

R. K. Nagaria

Keyword(s):

Power Consumption ◽

Power Supply ◽

Loading Condition ◽

Cmos Technology ◽

Clock Frequency ◽

Logic Function ◽

Output Node ◽

Switching Dynamic ◽

Power Delay Product ◽

Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽

10.3390/electronics9122033 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2033

Author(s):

Ahmed Elgreatly ◽

Ahmed Dessouki ◽

Hassan Mostafa ◽

Rania Abdalla ◽

El-sayed El-Rabaie

Keyword(s):

Power Consumption ◽

Software Defined Radio ◽

Dynamic Range ◽

Supply Voltage ◽

Cmos Technology ◽

The Body ◽

Analog To Digital Converters ◽

Clock Frequency ◽

Analog To Digital ◽

Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.1049-1050.687 ◽

2014 ◽

Vol 1049-1050 ◽

pp. 687-690

Author(s):

Yu Han Gao ◽

Ru Zhang Li ◽

Dong Bing Fu ◽

Yong Lu Wang ◽

Zheng Ping Zhang

Keyword(s):

High Speed ◽

Binary Code ◽

Sampling Rate ◽

Gray Code ◽

Cmos Technology ◽

Careful Consideration ◽

Analog To Digital ◽

Interleaved Adc ◽

Time Interleaved ◽

Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS

10.1142/s0218126613400252 ◽

2013 ◽

Vol 22 (10) ◽

pp. 1340025

Author(s):

TENG WANG ◽

LEI ZHAO ◽

ZI-YI HU ◽

ZHENG XIE ◽

XIN-AN WANG

Keyword(s):

Power Consumption ◽

Real Time ◽

Hardware Design ◽

Cmos Technology ◽

Vlsi Implementation ◽

Clock Frequency ◽

Hardware Cost ◽

Decomposition Approach ◽

Lower Power ◽

Decomposition Scheme

In this paper, a novel decomposition approach and VLSI implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders are proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements (AEs) which are comprised of only adders. Four types of AEs are developed and a pipelining hardware design is proposed to conduct the chroma interpolation with great hardware reuse. The proposed design was prototyped within a Xilinx Virtex6 XC6VLX240T FPGA with a clock frequency as high as 245 MHz. The proposed design was also synthesized with SMIC 130 nm CMOS technology with a clock frequency of 200 MHz, which could support a real-time HDTV application with less hardware cost and lower power consumption.

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽

10.3390/electronics8030305 ◽

2019 ◽

Vol 8 (3) ◽

pp. 305 ◽

Cited By ~ 1

Author(s):

Dong Wang ◽

Xiaoge Zhu ◽

Xuan Guo ◽

Jian Luan ◽

Lei Zhou ◽

...

Keyword(s):

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Sar Adc ◽

Oxide Semiconductor ◽

Power Measurement ◽

Cmos Process ◽

Analog To Digital ◽

Full Speed ◽

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598331 ◽

2016 ◽

Cited By ~ 4

Author(s):

Dante Gabriel Muratore ◽

Alper Akdikmen ◽

Edoardo Bonizzoni ◽

Franco Maloberti ◽

U-Fat Chio ◽

...

Keyword(s):

Single Channel ◽

Cmos Technology ◽

Sar Adc