MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit

2021 ◽  
Vol 24 (4) ◽  
pp. 311-321
Author(s):  
Gyan Prabhakar ◽  
Abhishek Vikram ◽  
Rajendra Pratap ◽  
R.K. Singh
Keyword(s):  
Charge Pump ◽  
Input Voltage ◽  
Cmos Process ◽  
Output Stage ◽  
Mos Capacitor ◽  
Silicon Area ◽  
Area Efficiency ◽  
Integrated Inductor ◽  
Lc Circuit ◽  
Ripple Cancellation

This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.

A Stable Mode-Selectable Oscillator with Variable Duty Cycle and High-Efficiency

2015 ◽  
Vol 24 (09) ◽  
pp. 1550132 ◽  
Author(s):  
Li-Ye Cheng ◽  
Xin-Quan Lai
Keyword(s):  
Duty Cycle ◽  
High Efficiency ◽  
Dynamic Performance ◽  
Operation Mode ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Process ◽  
Pump Efficiency ◽  
Stable Mode ◽  
Wide Range

A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V IN ) in all modes with low EMI.

scholarly journals A Novel CMOS reconfigurable rectifier for wearable piezoelectric energy harvesters

2021 ◽  
Vol 21 (1) ◽  
Author(s):  
Suany Vázquez-Valdés ◽  
Raúl Juárez-Aguirre ◽  
Rosa Woo-García ◽  
Primavera Argüelles-Lucho ◽  
Agustín Herrera-May ◽  
...  
Keyword(s):  
Conversion Efficiency ◽  
Textile Industry ◽  
Input Voltage ◽  
Human Motion ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Silicon Area ◽  
Energy Harvesters ◽  
Piezoelectric Energy

Wearable energy harvesters have potential application in the conversion of human-motion energy into electrical energy to power smart health-monitoring devices, the textile industry, smartwatches, and glasses. These energy harvesters require optimal rectifier circuits that maximize their charging efficiencies. In this study, we present the design of a novel complementary metal-oxide semiconductor (CMOS) reconfigurable rectifier for wearable piezoelectric energy harvesters that can increase their charging efficiencies. The designed rectifier is based on standard 0.18 µm CMOS process technology considering a geometrical pattern with a total silicon area of 54.765 µm x 86.355 µm. The proposed rectifier circuit has two transmission gates (TG) that are composed of four rectifier transistors with a charge of 45 kΩ, a minimum input voltage of 500 mV and a maximum voltage of 3.3 V. Results of numerical simulations of the rectifier performance indicate a voltage conversion efficiency of 99.4% and a power conversion efficiency up to 63.3%. The proposed rectifier can be used to increase the charging efficiency of wearable piezoelectric energy harvesters.

scholarly journals A Fully Integrated Clocked AC-DC Charge Pump for Mignetostrictive Vibration Energy Harvesting

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2194
Author(s):  
Hayato Kawauchi ◽  
Toru Tanzawa
Keyword(s):  
Output Power ◽  
Charge Pump ◽  
Input Voltage ◽  
Open Circuit ◽  
Vibration Energy ◽  
Cmos Process ◽  
Vibration Energy Harvesting ◽  
Fully Integrated ◽  
Energy Transducer ◽  
On Chip

This paper describes a clocked AC-DC charge pump to enable full integration of power converters into a sensor or radio frequency (RF) chip even with low open circuit voltage magnetostrictive vibration energy transducer operating at a low resonant frequency of 10 Hz to 1 kHz. The frequency of the clock to drive an AC-DC charge pump was up-converted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. A model of the system including the charge pump and vibration energy transducer is shown. It was validated by HSPICE simulation and measured, resulting in a prototype chip with an area of 0.11 mm2 fabricated in a 65 nm 1 V CMOS process. The fabricated charge pump was also measured together with a magnetostrictive transducer. The charge pump converted the power from the transducer to an output power of 4.2 μW at an output voltage of 2.0 V. The output power varied below 3% over a wide input frequency of 10 Hz to 100 kHz, which suggests that universal design of the clocked AC-DC charge pump can be used for transducers with different resonant frequencies. In a low-input voltage region below 0.8 V, the proposed circuit has higher output power compared with the conventional circuits.

scholarly journals A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1143
Author(s):  
Quanzhen Duan ◽  
Weidong Li ◽  
Shengming Huang ◽  
Yuemin Ding ◽  
Zhen Meng ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Input Voltage ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Chip Area ◽  
Linear Regulator

A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power voltage of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS transistors served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

scholarly journals A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 146
Author(s):  
Young-Joe Choe ◽  
Hyohyun Nam ◽  
Jung-Dong Park
Keyword(s):  
Maximum Load ◽  
Input Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Feed Forward ◽  
Power Supply Rejection Ratio ◽  
Wide Range ◽  
Low Dropout Regulator ◽  
Ldo Regulator ◽  
Ripple Cancellation

In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.

High-Efficiency Charge Pump LED Driver Circuit Design

2013 ◽  
Vol 389 ◽  
pp. 612-617 ◽  
Author(s):  
Yi Jiang Cao ◽  
Hao De ◽  
Jia Mu Cao ◽  
Xing Hua Tang ◽  
Qian Cui
Keyword(s):  
Electromagnetic Interference ◽  
High Efficiency ◽  
Circuit Simulation ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Process ◽  
Led Driver ◽  
Simulation Tools ◽  
Driver Circuit ◽  
Static Power

In this paper, Using CSMC 0.5μm CMOS process to design each sub-module, the circuit simulation, and adjustment and validation of parameters have been carried out by simulation tools. The low static power and high conversion efficiency charge pump LED driver circuit has been designed. The circuits nucleus module is adaptive charge pump (1x/1.5x/2x charge pump), to converse a wider range of input voltage to a constant output voltage with high efficiency. This circuit only needs some external capacitors, and dont need inductor. So it reduces EMI electromagnetic interference and application cost, etc.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Design of the variable frequency oscillator in DC-DC converter

Circuit World ◽  
2019 ◽  
Vol 45 (2) ◽  
pp. 80-85
Author(s):  
Tian Lei ◽  
Nan Gong ◽  
Li Wang ◽  
Qin Qin Li ◽  
Heng Wei Wang
Keyword(s):  
Supply Voltage ◽  
Operating Frequency ◽  
Maximum Deviation ◽  
Variable Frequency ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Output Stage ◽  
Content Type ◽  
Oscillator Frequency ◽  
Light Load

Purpose Because of the logic delay in the converter, the minimum turn on time of the switch is influenced by the constant time. When the inductor current gets to the threshold of the chip, the control signal will delay for a period. This makes the inductor current rising with the increasing of the clock and leads to the load current out of control. Thus, this paper aims to design an oscillator with a variable frequency protection function. Design/methodology/approach This paper presents an oscillator with the reducing frequency applied in the DC-DC converter. When the converter works normally, the operating frequency of the oscillator is 1.5 MHz. So the inductor current has enough time to decay and prevent the power transistor damaging. After the abnormal condition, the converter returns to the normal operating mode automatically. Findings Based on 0.5 µm CMOS process, simulated by the HSPICE, the simulation results shows that the frequency of the oscillator linearly decreases from 1.5 MHz to 380 KHz when the feedback voltage less than 0.2 V. The maximum deviation of the oscillator frequency is only 6 per cent from −50°C to 125°C within the power supply voltage of 2.7-5.5 V. Originality/value When the light load occurs at the output stage, the oscillator frequency will decrease as the load voltage drops. The test results shows that when the circuit works in the normal condition, the oscillator frequency is 1.5 MHz. When the load decreased, the operating frequency is dropped dramatically.

A 50 mV Fully-Integrated Self-Startup Circuit for Thermal Energy Harvesting

2017 ◽  
Vol 26 (12) ◽  
pp. 1750196 ◽  
Author(s):  
Yanzhao Ma ◽  
Yinghui Zou ◽  
Shengbing Zhang ◽  
Xiaoya Fan
Keyword(s):  
Energy Harvesting ◽  
Thermal Energy ◽  
Output Voltage ◽  
Charge Pump ◽  
Input Voltage ◽  
Fully Integrated ◽  
Input Capacitance ◽  
Low Input ◽  
Lc Oscillator ◽  
Thermal Energy Harvesting

A fully-integrated self-startup circuit with ultra-low voltage for thermal energy harvesting is presented in this paper. The converter is composed of an enhanced swing LC oscillator and a charge pump with decreased equivalent input capacitance. The LC oscillator has ultra-low input voltage and high output voltage swing, and the charge pump has a fast charging speed and small equivalent input capacitance. This circuit is designed with 0.18[Formula: see text][Formula: see text]m standard CMOS process. The simulation results show that the output voltage is in the range of 0.14[Formula: see text]V and 2.97[Formula: see text]V when the input voltage is changed from 50[Formula: see text]mV to 150[Formula: see text]mV. The output voltage could reach 2.87[Formula: see text]V at the input voltage of 150[Formula: see text]mV and the load of 1[Formula: see text]M[Formula: see text]. The maximum efficiency is in the range of 10.0% and 14.8% when the input voltage is changed from 0.2[Formula: see text]V to 0.4[Formula: see text]V. The circuit is suitable for thermoelectric energy harvesting to start with ultra-low input voltage.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

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