scholarly journals The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

Materials ◽  
2021 ◽  
Vol 14 (17) ◽  
pp. 4827
Author(s):  
Nianmin Hong ◽  
Yinong Zhang ◽  
Quan Sun ◽  
Wenjie Fan ◽  
Menglu Li ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Data Storage ◽  
Integrated Circuit ◽  
Porous Silica ◽  
Dielectric Materials ◽  
Interlayer Dielectric ◽  
Damascene Process ◽  
Key Issues ◽  
Deposition Processes ◽  
Low K

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

Low-K Porous Spin-On-Glass

1999 ◽  
Vol 565 ◽  
Author(s):  
Paul A. Kohl ◽  
Agnes Padovani ◽  
Michael Wedlake ◽  
Dhananjay Bhusari ◽  
Sue Ann ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Elevated Temperatures ◽  
Porous Silica ◽  
Dielectric Materials ◽  
Decomposition Products ◽  
Air Gaps ◽  
Low Dielectric ◽  
Polymer Decomposition ◽  
Low K ◽  
By Products

AbstractPreviously, the fabrication of air-gap structures for electrical interconnections was demonstrated using a sacrificial polymer encapsulated in conventional dielectric materials. The air-gaps were formed by thermally decomposing the sacrificial polymer and allowing the by-products to diffuse through the encapsulating dielectric. The diffusivity of the polymer decomposition products is adequate at elevated temperatures to allow the formation of air-gaps. This process was extended to form low dielectric constant, porous silica from commercially available methylsilsesquioxane (MSQ) by the addition of the sacrificial polymer to the MSQ. The porous MSQ film was thermally cured followed by decomposition of the NB at temperatures above 400°C. The dielectric constant of the MSQ was lowered from 2.7 to 2.3 by creating 70 nm pores in the MSQ. The voids created in the MSQ appeared to exhibit a closed-pore structure.

Novel Materials as Interlayer Low-K Dielectrics for CMOS Interconnect Applications

2011 ◽  
Vol 110-116 ◽  
pp. 5380-5383
Author(s):  
Tejas R. Naik ◽  
Veena R. Naik ◽  
Nisha P. Sarwade
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuits ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Novel Materials ◽  
Low Dielectric ◽  
Processing Properties ◽  
New Generation ◽  
Low K

Scaling down the integrated circuits has resulted in the arousal of number of problems like interaction between interconnect, crosstalk, time delay etc. These problems can be overcome by new designs and by use of corresponding novel materials, which may be a solution to these problems. In the present paper we try to put forward very recent development in the use of novel materials as interlayer dielectrics (ILDs) having low dielectric constant (k) for CMOS interconnects. The materials presented here are porous and hybrid organo-inorganic new generation interlayer dielectric materials possessing low dielectric constant and better processing properties.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

Intrinsic low dielectric behaviour of a highly thermally stable Sr-based metal–organic framework for interlayer dielectric materials

2014 ◽  
Vol 2 (19) ◽  
pp. 3762-3768 ◽  
Author(s):  
Muhammad Usman ◽  
Cheng-Hua Lee ◽  
Dung-Shing Hung ◽  
Shang-Fan Lee ◽  
Chih-Chieh Wang ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Organic Framework ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Water Molecules ◽  
Compound A ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Metal Organic ◽  
Organic Framework

A Sr-based metal–organic framework exhibits an intrinsic low dielectric constant after removing the water molecules. A low dielectric constant and high thermal stability make this compound a candidate for use as a low-k material.

Designing Ultra Low-k Dielectric Materials for Ease of Patterning

2010 ◽  
Vol 1249 ◽  
Author(s):  
George Andrew Antonelli ◽  
Gengwei Jiang ◽  
Mandyam Sriram ◽  
Kaushik Chattopadhyay ◽  
Wei Guo ◽  
...  
Keyword(s):  
Inductively Coupled Plasma ◽  
Ion Beam ◽  
Plasma Reactor ◽  
Dielectric Materials ◽  
Dielectric Constants ◽  
Interlayer Dielectric ◽  
Inductively Coupled ◽  
Inductively Coupled Plasma Reactor ◽  
Low K

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.

Siloxane Polymers as Low Dielectric Materials for Microelectronics

1995 ◽  
Vol 390 ◽  
Author(s):  
C. P. Wong
Keyword(s):  
Dielectric Constant ◽  
Three Dimensional ◽  
Signal Propagation ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Dimensional Structure ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
High Dielectric

ABSTRACTA modem VLSI device is a complicated three-dimensional structure that consists of multilayer metallization conductor lines which are separated with interlayer-dielectrics as insulation. This VLSI technology drives the IC device into sub-micron feature size that operates at ultra-fast speed (in excess of > 100 MHz). Passivation and interlayer dielectric materials are critical to the device performance due to the conductor signal propagation delay of the high dielectric constant of the material. Low dielectric constant materials are the preferred choice of materials for this reasons. These materials, such as Teflon® and siloxanes (silicones), are desirable because of their low dielectric constant (∈1) = 2.0, 2.7, respectively. This paper describes the use of a low dielectric constant siloxane polymer (silicone) as IC devices passivation layer material, its chemistry, material processes and reliability testing.

Thermal stability and structural evolution of low-K Fluorinated amorphous carbon during thermal annealing

1998 ◽  
Vol 511 ◽  
Author(s):  
Hongning Yang ◽  
Douglas J. Tweet ◽  
Yanjun Ma ◽  
Tue Nguyen ◽  
David R. Evans ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Dielectric Constant ◽  
Thermal Annealing ◽  
Structural Evolution ◽  
Fluorine Concentration ◽  
Interlayer Dielectric ◽  
Profound Impact ◽  
Initial Stage ◽  
Stress Changes ◽  
Low K

ABSTRACTHighly crosslinked a-F:C films can undergo a significant change after thermal annealing, where the film expands by ∼3%, the density reduces by ∼10% and the internal stress changes from compressive to tensile. The loss of fluorine concentration and the reduction of CF. are accompanied by the transition of (C-C, sp3) to (C=C, sp2) groups. After annealing, the dielectric constant is reduced and the leakage current increases slightly. Most importantly, these changes occur only at the initial stage of annealing. After the initial annealing, the a-F:C film tends to be thermally stable and retains reasonably good electrical properties as a low-k interlayer dielectric. The profound impact of these results on Cu/a-F:C integration will be briefly discussed.

Effects of Supercritical CO2 Drying and Photoresist Strip on Low-k Films

2003 ◽  
Vol 766 ◽  
Author(s):  
R.F. Reidy ◽  
Zhengping Zhang ◽  
R.A. Orozco-Teran ◽  
B.P. Gorman ◽  
D.W. Mueller
Keyword(s):  
Dielectric Constant ◽  
Porous Materials ◽  
Transport Properties ◽  
Supercritical Co2 ◽  
Polar Molecule ◽  
Interlayer Dielectric ◽  
Highly Porous Materials ◽  
Supercritical Co2 Drying ◽  
Low K ◽  
Highly Porous

AbstractFuture interlayer dielectric (ILD) requirements necessitate reductions in dielectric constant to 2.1 within four years. Due to gaseous-like transport properties and near liquid-like densities, supercritical methods have been developed to dry and strip resist from these highly porous materials. Although a non-polar molecule, the solvating capability of supercritical CO2 (SCCO2) can be tailored by varying pressure, temperature, and co-solvents. This flexibility has been employed to remove photoresist and moisture from porous low-k films. The results of these experiments have been characterized using FTIR, ellipsometry, and SEM.

Novel Periodic Nanoporous Silicate Glass With High Structural Stability as Low-k Thin Film

2002 ◽  
Vol 716 ◽  
Author(s):  
Yoshiaki Oku ◽  
Norikazu Nishiyama ◽  
Shunsuke Tanaka ◽  
Korekazu Ueyama ◽  
Nobuhiro Hata ◽  
...  
Keyword(s):  
Thin Film ◽  
Dielectric Constant ◽  
Structural Stability ◽  
Silicate Glass ◽  
Porous Silica ◽  
Silica Film ◽  
Peak Position ◽  
Nanoporous Silica ◽  
High Structural Stability ◽  
Low K

AbstractWe have recently developed novel periodic nanoporous silicate glass with high structural stability as low-k thin film by spin-coating method. Periodic porous silicate glass films developed so far cause structural shrinkage (10>∼20% or more) by annealing the spin-coated films. In this investigation we adopt vapor-phase TEOS (tetraethoxysilane)-treatment before anneal. Our novel nanoporous film shows little shift of XRD peak position after annealed at 673K, indicating both the ultimate mechanical strength and the minimization of stress in the interface between the prepared film and the underlying substrate. Such a shrinkage-free periodic nanoporous silica film can possess higher VBD (break down voltage) and lower ILeak (leakage current). In this article we estimate structural properties (including information on pores introduced intentionally) by XRD and TEM observation, and electrical properties (dielectric constant, VBD and ILeak) by IV and CV measurement of this special-treated periodic nanoporous silica film. The dielectric constant of the thus prepared periodic porous silica film with silylation after calcination was evaluated to be around 1.8 at 100kHz.

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