Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

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Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Sensors ◽

10.3390/s20174771 ◽

2020 ◽

Vol 20 (17) ◽

pp. 4771

Author(s):

Hyunyul Lim ◽

Minho Cheong ◽

Sungho Kang

Keyword(s):

Wireless Sensor Networks ◽

Sensor Networks ◽

Large Scale ◽

Vlsi Circuits ◽

Wireless Sensor ◽

Large Scale Integration ◽

Diagnosis Method ◽

Diagnosis Accuracy ◽

Scan Chain ◽

Scale Integration

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

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Contact Resistance and Methods for its Determination

MRS Proceedings ◽

10.1557/proc-18-361 ◽

1982 ◽

Vol 18 ◽

Cited By ~ 1

Author(s):

S. Simon Cohen

Keyword(s):

Integrated Circuits ◽

Contact Resistance ◽

Large Scale ◽

Ohmic Contacts ◽

Vlsi Circuits ◽

Single Element ◽

Large Scale Integration ◽

Proper Definition ◽

Definition Of ◽

Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

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Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays

MRS Bulletin ◽

10.1557/s0883769400036125 ◽

1996 ◽

Vol 21 (3) ◽

pp. 39-48 ◽

Cited By ~ 113

Author(s):

James S. Im ◽

Robert S. Sposili

Keyword(s):

Liquid Crystal ◽

Large Scale ◽

Liquid Crystal Display ◽

Liquid Crystal Displays ◽

Vlsi Circuits ◽

Active Matrix ◽

Large Scale Integration ◽

Scale Integration ◽

Matrix Liquid ◽

Si Wafer

The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.

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Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

10.5753/ctd.2017.3465 ◽

2017 ◽

Author(s):

Vinícius Dos Santos Livramento ◽

José Luís Güntzel

Keyword(s):

Integrated Circuits ◽

Large Scale ◽

Cmos Technology ◽

Vlsi Circuits ◽

Consumer Electronics ◽

Clock Frequency ◽

Wide Range ◽

Large Scale Integration ◽

On Chip ◽

Scale Integration

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

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Reliability-Aware Design of Spike-Event Neuromorphic Circuits

10.36227/techrxiv.15141537 ◽

2021 ◽

Author(s):

Jani Babu Shaik ◽

Siona Menezes Picardo ◽

Sonal Singhal ◽

Nilesh Goel

Keyword(s):

Large Scale ◽

Vlsi Circuits ◽

Performance Parameters ◽

Carrier Injection ◽

Neuromorphic Circuits ◽

Integrate And Fire ◽

Bias Temperature Instability ◽

Large Scale Integration ◽

Silicon Neurons ◽

Scale Integration

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

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Impact of driver size and interwire parasitics on crosstalk noise and delay

Journal of Engineering Design and Technology ◽

10.1108/jedt-08-2012-0036 ◽

2014 ◽

Vol 12 (4) ◽

pp. 475-490

Author(s):

Devendra Kumar Sharma ◽

Brajesh Kumar Kaushik ◽

R.K. Sharma

Keyword(s):

Integrated Circuit ◽

Large Scale ◽

Propagation Delay ◽

Combined Effects ◽

Crosstalk Noise ◽

Content Type ◽

Coupling Capacitance ◽

Large Scale Integration ◽

Scale Integration ◽

Coupling Parasitics

Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node. Findings – This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out. Originality/value – The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

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Wide operating window spin-torque majority gate towards large-scale integration of logic circuits

AIP Advances ◽

10.1063/1.5007758 ◽

2018 ◽

Vol 8 (5) ◽

pp. 055920 ◽

Cited By ~ 3

Author(s):

Adrien Vaysset ◽

Odysseas Zografos ◽

Mauricio Manfrini ◽

Dan Mocuta ◽

Iuliana P. Radu

Keyword(s):

Large Scale ◽

Logic Circuits ◽

Spin Torque ◽

Majority Gate ◽

Large Scale Integration ◽

Scale Integration ◽

Operating Window ◽

Wide Operating

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A Theoretical Modeling Analysis of Adapted Composite CNT Bundle for High-Speed VLSI Interconnect

10.20944/preprints202111.0286.v1 ◽

2021 ◽

Author(s):

Abu Bony Amin ◽

S M Shakil ◽

Muhammad Sana Ullah

Keyword(s):

Carbon Nanotube ◽

Behavioral Change ◽

High Speed ◽

Large Scale ◽

Propagation Delay ◽

Global Level ◽

Modeling Analysis ◽

Large Scale Integration ◽

To Come ◽

Scale Integration

The aroused quest to reduce the delay at interconnect level is the main urge of this paper to come across a configuration of Carbon Nanotube (CNT) bundle namely squarely packed bundle of composite CNTs. The approach, demonstrated in this paper, adapts the composite bundle to adopt for high speed Very Large Scale Integration (VLSI) interconnect with technology sizing down. To reduce the delay of the proposed configuration of composite CNT bundle, the behavioral change of Resistance (R), Inductance (L) and Capacitance (C) has been observed with respect to both width of the bundle and diameter of the CNTs in the bundle. Consequently, the performance of the modified bundle configuration is compared with previously developed configuration namely squarely packed bundle of dimorphic MWCNTs in terms of propagation delay and crosstalk delay at local, semiglobal and global level interconnect. The proposed bundle configuration is ultimately enacted as better one for 32nmand 16nmtechnology node and suitable for 7nmas well.

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Voltage contrast: A powerful tool for VLSI circuit diagnosis

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100074653 ◽

1983 ◽

Vol 41 ◽

pp. 164-167

Author(s):

A. R. Stivers

Keyword(s):

Integrated Circuit ◽

Large Scale ◽

Vlsi Circuits ◽

Current Drive ◽

Beam Voltage ◽

Capacitive Load ◽

Large Scale Integration ◽

High Resolution Images ◽

Voltage Contrast ◽

Scale Integration

The advent of very large scale integration (VLSI) presents many new problems for integrated circuit (I.C.) diagnosis. Some I.C.s have over 100,000 transistors with less than 100 external leads with which the transistors can be tested. The geometries are now as small as 3 μm, smaller than can be probed mechanically. Along with the size, node capacitance and current drive are also reduced making a probe's capacitive load very detrimental to rise-time measurements. New processes have many layers of interconnect, leaving more and more of the circuit below passivation and therefore inaccessible to a mechanical probe, even after the removal of scratch protection. VLSI challenges I.C. diagnosis with more internal circuitry that becomes smaller and less accessible to conventional probes.Voltage contrast is an electron beam voltage probing technique especially suited to VLSI circuits. A properly modified SEM, used in the voltage contrast mode, provides both high resolution images of circuit voltages and also voltage waveforms of particular nodes.

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