Floating Substrate Passive Voltage Contrast (FSPVC)

2006 ◽  
Author(s):  
Mark W. Jenkins ◽  
Paiboon Tangyunyong ◽  
Edward I. Cole ◽  
Jerry M. Soden ◽  
Jeremy A. Walraven ◽  
...  
Keyword(s):  
Electron Emission ◽  
Light Emission ◽  
Secondary Electron Emission ◽  
Gate Oxide ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
The Past ◽  
Soi Devices ◽  
Gate Oxide Short ◽  
Voltage Contrast

Abstract Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

A Novel Electrical Test by C-AFM to Differentiate Gate-to-S/D Gate Oxide Short From Non-Gate Oxide Short Defect in Real Products

2004 ◽  
Author(s):  
Cheng-Piao Lin ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting
Keyword(s):  
Atomic Force Microscopy ◽  
Short Path ◽  
Gate Oxide ◽  
Electrical Test ◽  
Force Microscopy ◽  
Atomic Force ◽  
Gate Oxide Short ◽  
Voltage Contrast

Abstract A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.

Failure Analysis from the Backside of a Die

2000 ◽  
Author(s):  
Silke Liebert
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Gate Oxide ◽  
Physical Analysis ◽  
Back Side ◽  
Bulk Silicon ◽  
Analysis Methods ◽  
On Chip ◽  
Voltage Contrast ◽  
Side Flow

Abstract A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using PEM are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an AFM tip for detection of interrupts within conductive interconnects are described.

Historical Introduction

1977 ◽  
Vol 35 ◽  
pp. 2-5
Author(s):  
R. D. Heidenreich
Keyword(s):  
Electron Emission ◽  
Secondary Electron ◽  
Secondary Electron Emission ◽  
50Th Anniversary ◽  
Secondary Emission ◽  
Wave Nature ◽  
Nobel Prize In Physics ◽  
Primary Electrons ◽  
The U.S ◽  
Mutual Agreement

This program has been organized by the EMSA to commensurate the 50th anniversary of the experimental verification of the wave nature of the electron. Davisson and Germer in the U.S. and Thomson and Reid in Britian accomplished this at about the same time. Their findings were published in Nature in 1927 by mutual agreement since their independent efforts had led to the same conclusion at about the same time. In 1937 Davisson and Thomson shared the Nobel Prize in physics for demonstrating the wave nature of the electron deduced in 1924 by Louis de Broglie.The Davisson experiments (1921-1927) were concerned with the angular distribution of secondary electron emission from nickel surfaces produced by 150 volt primary electrons. The motivation was the effect of secondary emission on the characteristics of vacuum tubes but significant deviations from the results expected for a corpuscular electron led to a diffraction interpretation suggested by Elasser in 1925.

SEM and Auger microanalysis studies of Cu-Be dynode surfaces at each activation condition

1978 ◽  
Vol 36 (1) ◽  
pp. 524-525
Author(s):  
T. Koshikawa ◽  
Y. Fujii ◽  
E. Sugata ◽  
F. Kanematsu
Keyword(s):  
Electron Emission ◽  
Secondary Electron ◽  
Secondary Electron Emission ◽  
Life Time ◽  
Activation Process ◽  
Beam Diameter ◽  
Activation Temperature ◽  
Electron Multiplier ◽  
Activation Condition ◽  
Activation Conditions

The Cu-Be alloys are widely used as the electron multiplier dynodes after the adequate activation process. But the structures and compositions of the elements on the activated surfaces were not studied clearly. The Cu-Be alloys are heated in the oxygen atmosphere in the usual activation techniques. The activation conditions, e.g. temperature and O2 pressure, affect strongly the secondary electron yield and life time of dynodes.In the present paper, the activated Cu-Be dynode surfaces at each condition are investigated with Scanning Auger Microanalyzer (SAM) (primary beam diameter: 3μmϕ) and SEM. The commercial Cu-Be(2%) alloys were polished with Cr2O3 powder, rinsed in the distilled water and set in the vacuum furnance.Two typical activation condition, i.e. activation temperature 730°C and 810°C in 5x10-3 Torr O2 pressure were chosen since the formation mechanism of the BeO film on the Cu-Be alloys was guessed to be very different at each temperature from the results of the secondary electron emission measurements.

SEM analysis of DC magnetron sputtered beryllium films

1988 ◽  
Vol 46 ◽  
pp. 960-961
Author(s):  
E. F. Lindsey ◽  
C. W. Price ◽  
E. L. Pierce ◽  
E. J. Hsieh
Keyword(s):  
Fine Structure ◽  
Electron Emission ◽  
Secondary Electron ◽  
Low Voltage ◽  
Ion Beam ◽  
Secondary Electron Emission ◽  
Sem Analysis ◽  
Fused Silica ◽  
Grain Structure ◽  
Silica Substrate

Columnar structures produced by DC magnetron sputtering can be altered by using RF biased sputtering or by exposing the film to nitrogen pulses during sputtering, and these techniques are being evaluated to refine the grain structure in sputtered beryllium films deposited on fused silica substrates. Beryllium is brittle, and fractures in sputtered beryllium films tend to be intergranular; therefore, a convenient technique to analyze grain structure in these films is to fracture the coated specimens and examine them in an SEM. However, fine structure in sputtered deposits is difficult to image in an SEM, and both the low density and the low secondary electron emission coefficient of beryllium seriously compound this problem. Secondary electron emission can be improved by coating beryllium with Au or Au-Pd, and coating also was required to overcome severe charging of the fused silica substrate even at low voltage. The coating structure can obliterate much of the fine structure in beryllium films, but reasonable results were obtained by using the high-resolution capability of an Hitachi S-800 SEM and either ion-beam coating with Au-Pd or carbon coating by thermal evaporation.

The advancement of silicon-on-insulator (SOI) devices and their basic properties

2020 ◽  
Vol 23 (3) ◽  
pp. 227-252
Author(s):  
T.E. Rudenko ◽  
◽  
A.N. Nazarov ◽  
V.S. Lysenko ◽  
◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Basic Properties ◽  
Soi Devices

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

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