scholarly journals A Potentiostat Readout Circuit with a Low-Noise and Mismatch-Tolerant Current Mirror Using Chopper Stabilization and Dynamic Element Matching for Electrochemical Sensors

2021 ◽  
Vol 11 (18) ◽  
pp. 8287
Author(s):  
Kyeongsik Nam ◽  
Gyuri Choi ◽  
Hyungseup Kim ◽  
Mookyoung Yoo ◽  
Hyoungho Ko
Keyword(s):  
Electrochemical Sensors ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Noise ◽  
Current Mirror ◽  
Readout Circuit ◽  
Dynamic Element Matching ◽  
Chopper Stabilization ◽  
Cascode Current Mirror ◽  
Dynamic Element

This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance amplifier (TIA), gain-boosted cascode current mirror, and a control amplifier (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 μm CMOS process and can measure the sensor current from 350 nA to 2.8 μA. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pARMS, and the power consumption was 287.9 μW with a 1.8 V power supply.

scholarly journals Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

2020 ◽  
Vol 10 (1) ◽  
pp. 348 ◽  
Author(s):  
Donggeun You ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Low Noise ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Frequency Noise ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chopper Stabilization ◽  
Total Power Consumption

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

scholarly journals Low-Noise Chopper-Stabilized Multi-Path Operational Amplifier with Nested Miller Compensation for High-Precision Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 281 ◽  
Author(s):  
Jaesung Kim ◽  
Hyungseup Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
High Precision ◽  
Operational Amplifier ◽  
High Frequency ◽  
Flicker Noise ◽  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Miller Compensation ◽  
Chopper Stabilization ◽  
Nested Miller Compensation

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm2. The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

Design of CMOS Amplifier Using New CCII Topologies

2011 ◽  
Vol 328-330 ◽  
pp. 1824-1827
Author(s):  
Li Cheng ◽  
Ning Li ◽  
Jia Jian Xi ◽  
Ning Yang
Keyword(s):  
High Performance ◽  
Current Conveyor ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Dynamic Element Matching ◽  
Output Resistance ◽  
Gain Error ◽  
Amplifier Design ◽  
Cmos Amplifier ◽  
Dynamic Element

A high-precision amplifier design in a stander 0.35μm CMOS process was proposed. This design obtains a high-performance by proper application of dynamic element matching to a second generation current conveyor (CCII). In comparison with the traditional CMOS circuits, the proposed approach can not only increase the output swing and decrease output resistance but also compensate the effect of the input offset and 1/fnoise voltage. The simulation results show that the gain error is reduced 38~50 times than the traditional amplifier, and the precision is significantly improved. So the proposed circuit is suitable for the design of special amplifiers used in various detections and signal mediation.

scholarly journals A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 241 ◽  
Author(s):  
Min Qi ◽  
An-qiang Guo ◽  
Dong-hai Qiao
Keyword(s):  
Integrated Circuit ◽  
Sampling Technique ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Frequency Noise ◽  
Voltage Reference ◽  
Noise Floor ◽  
Mems Sensor ◽  
Output Noise

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

scholarly journals Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7280
Author(s):  
Xiangyu Li ◽  
Yangong Zheng ◽  
Xiangyan Kong ◽  
Yupeng Liu ◽  
Danling Tang
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
High Signal ◽  
Cmos Process ◽  
Frequency Noise ◽  
Interface Circuit ◽  
Noise Characteristics ◽  
Mems Accelerometers

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.

A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices

2019 ◽  
Vol 15 (3) ◽  
pp. 315-322
Author(s):  
Manu Chilukuri ◽  
Sungyong Jung ◽  
Hoon-Ju Chung
Keyword(s):  
Hearing Aid ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Charge Amplifier ◽  
Front End ◽  
Analog Front End ◽  
A Charge ◽  
Cascode Current Mirror

In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.

A 3.6 μW 60 nV/sqrtHz Capacitively-Coupled Instrumentation Amplifier for Biopotential Signal Recordings

2015 ◽  
Vol 24 (06) ◽  
pp. 1550089 ◽  
Author(s):  
Yin Zhou ◽  
Xiaobo Wu ◽  
Peng Sun ◽  
Menglian Zhao
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Frequency Noise ◽  
Noise Power ◽  
Current Feedback ◽  
Common Mode ◽  
Capacitively Coupled ◽  
Offset Voltage

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm2 core area and consumes 3.6 μA from a 1 V supply.

A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL

2014 ◽  
Vol 33 (9) ◽  
pp. 2709-2718 ◽  
Author(s):  
Umakanta Nanda ◽  
Debiprasad Priyabrata Acharya ◽  
Sarat Kumar Patra
Keyword(s):  
Charge Pump ◽  
Low Noise ◽  
Current Mirror ◽  
Transmission Gate ◽  
Cascode Current Mirror
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